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vhdl code for counterand detemines how counter
works
vhdl code for counterand detemines how counter
works
- 2023-03-20 20:40:03下载
- 积分:1
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FPGA代码,Designing_with_Quartus_II_Exercises_Ver11_v4_2.doc
FPGA代码,Designing_with_Quartus_II_Exercises_Ver11_v4_2.doc-FPGA code Designing_with_Quartus_II_Exercises_Ver1 1_v4_2.doc
- 2023-03-14 03:35:04下载
- 积分:1
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pin_lv1
一个简易的频率计,主要用检测在一定范围内的频率,当然频率过大会有误差(A simple frequency meter, mainly used for testing in a range of frequencies, of course, frequency of errors over the General Assembly)
- 2010-06-05 10:30:56下载
- 积分:1
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full adder in vhdl of 4 bits
full adder in vhdl of 4 bits
- 2022-02-01 04:44:39下载
- 积分:1
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2-ADC—单通道(DMA读取)
说明: STM32F103 ADC 通过DMA进行读取(STM32F103 ADC reads by DMA)
- 2020-08-20 15:36:26下载
- 积分:1
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altera的ip核,在sopcbuilder中添加后,在niosII IDE中可以用一条语句实现,音频解码的输出。...
altera的ip核,在sopcbuilder中添加后,在niosII IDE中可以用一条语句实现,音频解码的输出。-altera
- 2022-03-05 12:43:51下载
- 积分:1
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fpga实例程序代码
关于FPGA的一些例程,包括CORDIC数字计算机的设计,RS(204,188)译码器的设计等。(Some routines on FPGA include the design of CORDIC digital computers, the design of RS (204188) decoders, etc.)
- 2018-07-21 19:08:25下载
- 积分:1
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在quartus中使用IP核的实际例子与流程
在quartus中使用IP核的实际例子与流程-The use of IP in the Quartus practical examples and nuclear flow
- 2022-08-07 01:33:34下载
- 积分:1
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4通道12位AD芯片 AD7862控制模块,VHDL源代码,适于单次转换采样,250K采样率....
4通道12位AD芯片 AD7862控制模块,VHDL源代码,适于单次转换采样,250K采样率.-4-channel 12-bit AD chip AD7862 control module, VHDL source code, suitable for single conversion sampling, 250K sampling rate.
- 2022-04-20 03:37:20下载
- 积分:1
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FIFO
Verilog HDL语言编写异步FIFO(Verilog HDL language, asynchronous FIFO)
- 2012-05-31 15:13:21下载
- 积分:1