-
fulladd
this files in Quartus2 are fulladder
- 2016-05-17 16:38:42下载
- 积分：1
-
The document may download to FPGA chip to complete the clock divider,serial
本文件是可以直接使用下载到FPGA里面使用，里面包含时钟分频电路，串并转换和并串转换电路，多通道信号加权的乘加电路等。-The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation
- 2022-09-03 00:05:03下载
- 积分：1
-
0702
七段数码管显示数字时 使用VHDL语言编写(VHDL The seven-segment LED display digital clock)
- 2013-03-25 22:31:09下载
- 积分：1
-
ad0809
adc0809 转换，verilog代码(adc0809 conversion, verilog code)
- 2020-12-21 11:09:08下载
- 积分：1
-
10_ImageEdge
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像边缘提取(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image edge extraction)
- 2020-10-23 20:27:22下载
- 积分：1
-
ahb2apb-master
ahb to apb master and slave
- 2018-03-06 00:27:56下载
- 积分：1
-
just division the clock into 2
just division the clock into 2
- 2022-01-26 05:48:15下载
- 积分：1
-
LCD1602测试程序
实现对LCD1602的Verilog HDL编程(the program for LCD1602 based on Verilog HDL)
- 2020-06-23 21:00:01下载
- 积分：1
-
8051 VHDL核心，内有说明，很详细，值得下载…
8051单片机VHDL内核,内有说明,很详细,值得下载-8051 VHDL core, which has made it clear that, in great detail, it is worth downloading
- 2022-07-08 17:52:49下载
- 积分：1
-
jtag
verilog语言编写的jtag（边界扫描模块），初学的时候可以看看(verilog language jtag (boundary scan module), a novice when you can look)
- 2021-04-27 14:38:44下载
- 积分：1
