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that I wrote four string and turn ISE code In xilinx Spartan3E debugging has bee...
这是我自己写的4位并转串ISE代码,在xilinx Spartan3E 上已经调试成功,拿出来与大家分享!-that I wrote four string and turn ISE code In xilinx Spartan3E debugging has been successful, with the show to share with you!
- 2022-02-14 20:17:51下载
- 积分:1
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华为经典FPGA设计全套入门技巧
说明: 华为FPGA设计全套资料,学习FPGA的朋友可以下载看看。(Huawei FPGA design a full set of materials, friends learning FPGA can download and see.)
- 2019-04-02 13:54:48下载
- 积分:1
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Verilog代码。注册成功,对FPGA的使用标准单元库…
verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
- 2022-01-31 00:50:36下载
- 积分:1
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FPGA实现Jpeg压缩,和视频采集程序
说明: FPGA实现Jpeg压缩,和视频采集程序(Zynq - Main - register access Mio)
- 2020-03-13 23:25:40下载
- 积分:1
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8位数字显示的简易频率计
(1)能够测试10HZ~10MHZ的方波信号;
(2)电路输入的基准时钟为1HZ,要求测量值以8421BCD码形式输出;
(3)系统有复位键;
(4)采用分层次分模块的方法,用Verilog HDL进行设计,并对各个模块写出测试代码;
(5)具体参照说明文档(包含源代码,仿真图,测试波形,详细的设计说明)(A square wave signal capable of testing 10HZ~10MHZ;
(2) the reference clock input by the circuit is 1HZ, and the measured value is output in the form of 8421BCD code;
(3) the system has a reset key;
(4) adopt the method of layering sub sub module and design with Verilog HDL;
(5) write test simulation program.)
- 2020-12-02 02:59:26下载
- 积分:1
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shift_regeister
用blockram实现移位寄存器,开发语言为verilog hdl(Shift register with blockram achieve the development language for the verilog hdl)
- 2020-08-13 22:18:29下载
- 积分:1
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VHDL
VHDL上百实例 包括 ADDER LATCH FIPPER AND ETC..(VHDL hundreds of examples, including ADDER LATCH FIPPER AND ETC ..)
- 2010-11-22 05:15:29下载
- 积分:1
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rs232_receiver
RS232接收程序 无奇偶校验位 并行输出8位数据与data_ready数据准备好信号(RS232 receive procedures without parity 8-bit parallel output data and data ready signal data_ready)
- 2009-07-06 19:56:52下载
- 积分:1
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CORDIC 代码
Xilinx CORDIC 算法 MATLAB Verilog仿真(arctan.m Kn.m sin_cos.m MATLAB Verilog)
- 2019-03-27 09:53:35下载
- 积分:1
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cntl_ddr3(xilinx)
xilinx ddr3最新VHDL代码,通过调试(xilinx ddr3 latest VHDL code through debugging)
- 2007-12-05 23:03:10下载
- 积分:1