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VHDL-the-count
利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发
时钟，计数器进行加计数，并利用数码管进行显示，当计数到9999 时，从0 开始重新计数(Use of VHDL hardware description language design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger
The clock, counter add count, and use digital pipes to show that when the count to 9999, starting from 0 to count
)
- 2012-01-13 14:01:38下载
- 积分：1
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CLZ_32bit
前导零的计算 (Calculation of leading zeros)
- 2021-03-31 21:29:09下载
- 积分：1
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read-string-from-FLASH
read data of type character from flash memory
- 2013-09-08 03:49:15下载
- 积分：1
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VHDL
控制电话信令
完成忙碌 等待 回铃音振铃等(Signaling complete control over telephone ring so busy waiting ringback tone)
- 2010-10-22 20:11:38下载
- 积分：1
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DDR2_hardcore_userguide
xillinx Spartan6 FPGA DDR 接口设计指南(xillinx Spartan6 FPGA DDR Interface Design Guidelines)
- 2009-11-23 10:18:28下载
- 积分：1
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sram
FPGA控制SRAM读写时序源码，代码桂发，新手一看就懂(FPGA control SRAM write timing source code Guifa novice understand at a glance)
- 2020-06-30 03:00:01下载
- 积分：1
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ControlUnit
Control Unit VHDL code. Xilinx Spartan 3E board
- 2012-03-15 13:29:40下载
- 积分：1
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ddr3_sun
说明： 使用DDR3IP核进行仿真，写入读取数据(Using DDR3IP core to simulate, write and read data)
- 2021-01-07 00:48:53下载
- 积分：1
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本程序为24小时计时器，稳定无误差。简单好用，是Verilog HDL语言初学者的指引。...
本程序为24小时计时器，稳定无误差。简单好用，是Verilog HDL语言初学者的指引。-This procedure for 24-hour timer, stable error-free. Easy-to-use, is the Verilog HDL language beginners guide.
- 2022-07-20 09:46:32下载
- 积分：1
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This is is a bridge IP core to interface the Tensilica PIF bus protocol with the...
This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
- 2022-04-07 07:47:24下载
- 积分：1
