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tanchishe-QuartusII
VGA显示FPGA实现的VHDL语言的贪吃蛇游戏设计
本设计分为6个模块主要是扫描模块 VGA现实和控制模块 游戏设计的模块 电源模块等
用QUARTUS2仿真运行(VGA display FPGA VHDL language to realize the Snake game design
The design is divided into six modules mainly scanning module VGA module power module and control module reality game design, etc.
Simulation run with QUARTUS2)
- 2020-11-06 10:09:50下载
- 积分：1
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Modulation
产生长度为100的随机二进制序列
发送载波频率为10倍比特率，画出过采样率为100倍符号率的BPSK调制波形（前10个比特） ，及其功率谱
相干解调时假设收发频率相位相同，画出x(t) 的波形，假设低通滤波器的冲激响应为连续10个1（其余为0），或连续12个1 （其余为0） ，分别画出两种滤波器下的y(t)，及判决输出（前10个比特）
接收载波频率为10.05倍比特率，初相位相同，画出x(t) 的波形，假设低通滤波器的冲激响应为连续10个1，画出两种滤波器下的y(t)，及判决输出（前20个比特）
采用DPSK及延时差分相干解调，载波频率为10倍比特率，画出a, b, c, d点的波形（前10个比特）
DPSK及延时差分相干解调，载波频率为10.25倍比特率时，画出a, b, c, d点的波形（前10个比特）
DPSK及延时差分相干解调，载波频率为10.5倍比特率时，画出a, b, c, d点的波形（前10个比特）
(Produce random binary sequence of length 100
The transmission carrier frequency is 10 times the bit rate, draw a sampling rate of 100 times the symbol rate of the BPSK modulation waveform (first 10 bits), its power spectrum
Coherent demodulation of assuming the same as the phase of the transmitting and receiving frequencies, and draw the waveform x (t), assuming that the impulse response of the low pass filter 10 consecutive 1 (the remainder is 0), or 12 consecutive 1 (the remainder is 0), y (t) is drawn under the two filters respectively, and the decision output (10 bits)
The received carrier frequency is 10.05 times the bit rate, the same initial phase, draw the waveform x (t), assuming that the impulse response of the low pass filter of 10 consecutive 1, shown under two filter y (t), and decision output (20 bits)
DPSK and delay differential coherent demodulation, the carrier frequency is 10 times the bit rate, draw a, b, c, d point of the waveform (first 10 bits)
DPSK and delay)
- 2020-12-14 08:19:14下载
- 积分：1
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Coding Style
良好的Coding Style能减少Bug，减少锁存器出现的可能以及其他隐藏逻辑错误，也有助于减小芯片面积或所用资源(Good Coding Style can reduce Bug, reduce the possibility of latches and other hidden logic errors, and also help to reduce chip area or resources used.)
- 2020-06-17 12:00:01下载
- 积分：1
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S6_VGA
1。源文件保存在src目录，QII的工程文件保存在Proj目录；
2。程序实现的功能是在VGA显示器上显示彩色条纹，共8种颜色，
可以使用嵌入式逻辑分析仪观测信号；
3。modelsim仿真文件在proj--simulation--modelsim中(1. The source file is saved in the src directory QII project file is saved in the directory Proj 2. The functionality of the program is displayed on a VGA monitor color stripes, 8 colors, you can use the embedded logic analyzer observed signals 3. the modelsim simulation files in the proj- simulation- modelsim)
- 2012-11-04 18:26:48下载
- 积分：1
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Verilog 编写的ISP1362的控制器IP核，altera公司DE2系统中的源程序
Verilog 编写的ISP1362的控制器IP核，altera公司DE2系统中的源程序-Verilog prepared ISP1362 controller IP core, altera company source DE2 System
- 2022-07-27 16:33:17下载
- 积分：1
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fjq1
介绍了在数字语音通信中, 利用在系统可编程技术和复杂可编程逻辑器件CPLD, 实现了数字语音的复接和分接
对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。实际应用结果表明, 系统工作稳
定可靠, 设计是成功的。(Describes the digital voice communications, the use of in-system programmable technical and complex programmable logic device CPLD, to achieve the digital voice multiplexer and demultiplexer for the single steady state in which the digital circuit and digital phase locked loop extraction bit synchronization signals are also carried out a detailed design specification. The practical application results show that the system works stable and reliable design is successful.)
- 2020-12-01 10:39:28下载
- 积分：1
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xilinx xc9572 cpld 实现的伺服电机控制器，电机控制输出，和增量编码器读取。...
xilinx xc9572 cpld 实现的伺服电机控制器，电机控制输出，和增量编码器读取。-Xilinx xc9572 cpld achieve servo motor controller, motor control output, Incremental encoder and the reader.
- 2022-07-13 06:40:13下载
- 积分：1
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VGA altera detailed description of the official routine Verilog code for a very...
详细介绍了VGA官方例程Verilog代码，非常好很实用
- 2022-08-21 17:43:09下载
- 积分：1
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pc_cfr_test_v3_1c
一个关于降低现代通信系统中高峰均比信号的matlab算法，对于研究数字预失真基于FPGA实现的有一定作用！(A modern communication system on the lower than the peak signal matlab algorithm for FPGA-based study of digital pre-distortion to achieve a certain effect!
)
- 2011-07-07 22:01:17下载
- 积分：1
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FPGAmidxilinx
基于FPGA的快速中值滤波算法,主要使用的语言是verilog 本文没有程序(FPGA-based fast median filtering algorithm, the main language used in this article does not process verilog)
- 2010-02-27 12:40:32下载
- 积分：1
