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bankorder
说明： 银行排队系统的VHDL程序实现，可以实现排队顾客自动取号，查看前面排队人数，银行服务柜台号等。(Bank queuing system VHDL program can be achieved automatically check its customers lined up to view the queue in front of the number of its banking services, such as counters.)
- 2008-11-28 15:49:49下载
- 积分：1
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FPGA_PSK
说明： 可以实现2PSK的信号调制，已经过Modelsim波形仿真(It can realize 2PSK signal modulation and has been simulated by Modelsim waveform.)
- 2019-05-09 16:29:17下载
- 积分：1
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fft_16
16点FFT，简单易理解，适合初学者了解(16 point FFT, simple and easy to understand, suitable for beginners to understand)
- 2018-05-07 16:20:10下载
- 积分：1
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clk_generator
时钟分频代码，PWM产生 RTL 源代码。(clock divider，PWM generator RTL Source Code)
- 2013-08-18 09:29:42下载
- 积分：1
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daima
Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。
模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期输出1地址的[0]位和0地址的[7：6]位，直至将存储器中64x8数据全部输出。若最后一组不足三位，则高位补0。
(Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)
- 2014-12-11 20:16:04下载
- 积分：1
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new
说明： 通过spi实现加速度计adxl357读取xyz三轴方向的加速度值(Accelerometers adxl357 read the acceleration value of XYZ three-axis direction through SPI)
- 2021-03-23 08:49:15下载
- 积分：1
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Vpwm
按键可调占空比的PWM波产生程序。语言：VHDL(Button adjustable duty cycle of the PWM wave generator. Language: VHDL)
- 2013-07-30 12:30:58下载
- 积分：1
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TFT_CTRL_800_480_16bit
文件用于驱动TFT屏，分辨率800*400，平台为quartus13，芯片为cycloneIV(The file is used to drive the TFT screen with a resolution of 800*400. The platform is quartus 13 and the chip is cyclone IV.)
- 2019-04-12 09:22:29下载
- 积分：1
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Embedded System multiplier test report including source code language used VHDl
嵌入式系统的乘法器试验报告 包括源代码 用VHDl语言编写-Embedded System multiplier test report including source code language used VHDl
- 2022-03-26 04:15:28下载
- 积分：1
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mips3
Modelsim+DC开发的4级流水线结构的MIPS CPU(mips 4level cpu)
- 2020-08-08 11:18:30下载
- 积分：1
