-
VerilogHDLshejifengpingqihe32weijishuqi
本文件介绍的是用VerilogHDL语言设计分频器和32位计数器.(This paper presents the design using Verilog HDL language Frequency Divider and 32 counters.)
- 2007-01-14 17:33:50下载
- 积分:1
-
Great guide for writing VHDL
Great guide for writing VHDL
- 2023-05-21 15:20:03下载
- 积分:1
-
vga
vga,显示彩条,及其简单易懂,适合初学(vga, display color bars, and its easy-to-understand, suitable for beginners)
- 2012-10-10 21:10:15下载
- 积分:1
-
MIPSTOP
说明: misp顶层文件,verilog实现misp架构,并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)
- 2020-06-18 04:40:02下载
- 积分:1
-
is61lv25616 (1)
verilog测试,fpga测试片外sramis61lv25616,256个k个字,16位,比较难调(it is fpga is 61lv25616 simple verilog program,complete sram read and write.it can read and write .)
- 2020-12-09 15:39:18下载
- 积分:1
-
Tmu_ni_dian_yh
这个课程设计的题目是模拟电压采集电路路与程序设计,报告书的内容都比较详细.
(The topics of this course design is an analog voltage acquisition circuit Road and program design, the contents of the report are more detailed.)
- 2012-07-19 09:23:07下载
- 积分:1
-
Advanced-FPGA-Design
高级FPGA设计__结构、实现和优化,中文翻译版(Advanced FPGA Design- Architecture, Implementation, and Optimization)
- 2021-04-01 11:09:08下载
- 积分:1
-
This tutorial presents some basic concepts that can be helpful in debugging of a...
This tutorial presents some basic concepts that can be helpful in debugging of application programs written in the Nios II assembly language, which run on Altera’s DE2 boards.
- 2022-08-19 12:45:10下载
- 积分:1
-
伪随机二进制序列无符号 17 位计数器
这通过反馈来实现一个 17 位伪随机的无符号计数器异或的位 0 和 3。 注意 ︰ 如果也绝不是独家使用相反,这会反相平行的位模式 & 这将意味着所有位都零是一种有效模式和所有那些不都是有效。 目前所有的都是有效的。
- 2022-02-15 14:03:54下载
- 积分:1
-
四位数字乘法器,在quartus8.0下仿真时序图
四位数字乘法器,在quartus8.0下仿真时序图 -mult4
- 2023-09-04 20:20:03下载
- 积分:1