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clock_smg
自己做的数码管显示的时钟 一个非常简单的FPGA时钟 用累加做的(To do their own digital display clock of the FPGA clock is a very simple to do with the cumulative)
- 2011-09-27 21:07:54下载
- 积分：1
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JTAG_Example0_Verilog
一个Verilog的JTAG程序例子，包括完整的说明文档和源文件。(tap_top.v
This file is part of the JTAG Test Access Port (TAP)
http://www.opencores.org/projects/jtag/
Author(s): Igor Mohor (igorm@opencores.org))
- 2021-04-27 13:48:44下载
- 积分：1
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DE2_CCD
说明： 此程序用来实现图像的采集和帧数的计算功能。(Image acquisition and calculation of the number of frames.)
- 2011-04-17 09:43:37下载
- 积分：1
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udp
说明： 网口UDP的FPGA仿真代码，经过测试能够实现预想功能(etherneit udp verilog fpga code)
- 2020-05-26 21:55:04下载
- 积分：1
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comp
The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
- 2012-06-05 23:16:25下载
- 积分：1
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ps2接口源程序。标准的键盘和鼠标接口，在Xilinx SpartanII XC2S200 实验板上通过验证...
ps2接口源程序。标准的键盘和鼠标接口，在Xilinx SpartanII XC2S200 实验板上通过验证-ps2 interface source. Standard keyboard and mouse interface, in the experiments on-board Xilinx SpartanII XC2S200 validated
- 2023-03-24 22:15:03下载
- 积分：1
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I2C配置tvp5150用VHDL写的
I2C配置tvp5150用VHDL写的 -I2C configuration tvp5150 written using VHDL
- 2023-05-02 14:30:04下载
- 积分：1
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Huffman_enc_dec
Huffman encoder decoder verilog
- 2021-03-21 00:49:17下载
- 积分：1
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atom.2007.12.tar
Cores are generated from Confluence a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C
- 2008-05-12 10:13:23下载
- 积分：1
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用verilog HDL语言，通过一个4位移位寄存器实现一个信号转化为HDB3码并进行测试...
用verilog HDL语言，通过一个4位移位寄存器实现一个信号转化为HDB3码并进行测试
-Using verilog HDL language, through a 4-bit shift register realization of a signal into HDB3 code and test
- 2023-05-23 03:15:03下载
- 积分：1
