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chaotic_1d
说明： 一维超混沌随机数的生成verilg，还有testbench仿真激励，modelsim的仿真工程。(The generation of one-dimensional hyperchaotic random number verilg, testbench simulation stimulation and Modelsim simulation engineering.)
- 2020-05-11 12:45:42下载
- 积分：1
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The number of organ controller Verilog code, with English Notes.
数字电子琴控制器的ＶＥＲＩＬＯＧ代码，含中文注释．-The number of organ controller Verilog code, with English Notes.
- 2022-02-28 22:36:52下载
- 积分：1
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VHDL38decoder
VHDL 语言实现 38译码器 文件中包括 程序 源代码 还有 testbench 测试程序(38 decoder VHDL language implementation, including program source code file, there are testbench test procedures)
- 2020-06-29 23:40:03下载
- 积分：1
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816-1681
SPARC Assembly Language Reference
Manual
- 2014-09-20 23:42:07下载
- 积分：1
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fpga_debounce_filter
fpga debounce filter code in vhdl
- 2009-10-02 18:48:22下载
- 积分：1
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用verilong hdl语言编写的数据采样程序，A/D采用的是TLC5260
用verilong hdl语言编写的数据采样程序，A/D采用的是TLC5260-Verilong hdl language used data sampling procedures, A/D using the TLC5260
- 2023-04-01 09:25:04下载
- 积分：1
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2
说明： Objects forming possible solution within original problem context are called phenotypes, their encoding, the individuals within the GA, are called genotypes.
The representation step specifies the mapping the phenotypes onto a set of genotypes.
Candidate solution, phenotype and individual are used to denotes points of the space of possible solutions. This space is called phenotype space.
Chromosome, and individual can be used for points in the genotye space.
Elements of a chromosome are called genes. A value of a gene is called an allele.
Variation Operators
The role of variation operators is to create new individuals old ones. Variation operators form the implementation of the elementary steps with the search space.
- 2014-12-22 22:54:47下载
- 积分：1
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俄罗斯方块（Xilinx版）
说明： 用verilog语言开发俄罗斯方块小游戏(Developing Tetris game with Verilog language)
- 2020-11-27 08:47:38下载
- 积分：1
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csbar(3) : X"E0000" to X"E01FF"
-- M68008 Address Decoder
-- Address decoder for the m68008
-- asbar must be 0 to enable any output
-- csbar(0) : X"00000" to X"01FFF"
-- csbar(1) : X"40000" to X"43FFF"
-- csbar(2) : X"08000" to X"0AFFF"
-- csbar(3) : X"E0000" to X"E01FF"
-- download from www.pld.com.cn & www.fpga.com.cn
--- M68008 Address Decoder-- Address decod er for the m68008-- 0 asbar must be to enable any o utput-- csbar (0) : X "00000" to X "01FFF"-- csbar (1) : X "40000" to X "43FFF"-- csbar (2) : X "08000" to X "0AFFF"-- csbar (3) : X "E0000" to X "E01FF"-- download from www.pld. com.cn
- 2022-02-26 21:53:57下载
- 积分：1
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vga_ctl_640x480
VGA 640x480 driver in verilog
- 2010-08-16 02:48:43下载
- 积分：1
