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使用VHDL语言，对Altera公司的DE2开发板进行开发，本例实现了对板上7段数码管的显示，在niosiiIDE上基于硬件实现小灯的循环亮灭...
使用VHDL语言，对Altera公司的DE2开发板进行开发，本例实现了对板上7段数码管的显示，在niosiiIDE上基于硬件实现小灯的循环亮灭-Using VHDL language, on Altera s DE2 development board for development, which in this case the realization of paragraph 7 of the on-board digital tube display, in niosiiIDE hardware implementation based on a small circle of bright lights out
- 2022-03-17 06:00:39下载
- 积分：1
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adder
说明： 通过四个半加器的互联，来实现四位加法器的电路结构(Through the interconnection of four and a half adder to achieve the four adder circuit)
- 2011-02-20 15:17:15下载
- 积分：1
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ALTERA上DE2平台，利用内部50M Hz时钟，在数码管模拟显示时间(时分秒)。
ALTERA上DE2平台，利用内部50M Hz时钟，在数码管模拟显示时间(时分秒)。-ALTERA on DE2 platform, using internal 50M Hz clock, in the digital control simulation show time (hours minutes and seconds).
- 2022-04-17 01:14:39下载
- 积分：1
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modelsim设计的可调占空比的方波程式
modelsim设计的可调占空比的方波程式-modelsim designed adjustable duty cycle of the square wave program
- 2022-09-02 05:05:03下载
- 积分：1
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VHDL由IEEE 1076标准定义的，IEEE标准的VHDL语言参考人…
VHDL is defined by IEEE Standard 1076, IEEE Standard VHDL Language Reference Manual (the VHDL LRM). The original standard was approved in 1987. IEEE procedures require that standards be periodically reviewed and either reaffirmed or revised. The VHDL standard was revised in 1993, 2000, and 2002. In each revision, new language features were added and some existing features enhanced. The aim in each revision was to improve the language as a tool for design and verification of digital systems.
Since the 2002 revision, there have two parallel efforts to further develop the language. The first was the VHDL Procedural Interface (VHPI) Task Force, a subcommittee of the IEEE P1076 Working Group. The VHPI Task Force prepared an interim amendment to the standard, formally approved by IEEE in March 2007. The amendment is titled IEEE 1076c, Standard VHDL Language Reference Manual―Amendment 1: Procedural Language Application Interface.
- 2023-05-31 06:40:03下载
- 积分：1
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基于FPGA的乐曲发生器电路设计 附含源代码（quartersii环境下运行）...
基于FPGA的乐曲发生器电路设计 附含源代码（quartersii环境下运行）-FPGA-based circuit design of the music generator containing the source code is attached (quartersii environment to run)
- 2022-02-16 04:27:54下载
- 积分：1
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CORDIC 代码
Xilinx CORDIC 算法 MATLAB Verilog仿真(arctan.m Kn.m sin_cos.m MATLAB Verilog)
- 2019-03-27 09:53:35下载
- 积分：1
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基于VHDL的I2C程序0004,很不错的论文及程序，，大家快下啊
基于VHDL的I2C程序0004,很不错的论文及程序，，大家快下啊-based on the I2C procedures VHDL 0004, a very good paper and procedures, we quickly under ah
- 2022-02-13 02:05:07下载
- 积分：1
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h_adder
ise13.2环境下VHDL编写的半加器器+仿真波形(ise13.2 environment half adder in VHDL simulation waveform control+)
- 2013-06-01 13:40:03下载
- 积分：1
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pl_read_write_ps_ddr
说明： PL 和 PS 的高效交互是 zynq 7000 soc 开发的重中之重，常常需要将 PL 端的大量数据实时送到 PS 端处理，或者将 PS 端处理结果实时送到 PL 端处理，但是各种协议非常麻烦，灵活性也比较差，直接通过 AXI 总线来读写 PS 端 ddr 的数据，这里面涉及到 AXI4 协议，vivado 的 FPGA 调试等。(The efficient interaction between PL and PS is the top priority of zynq 7000 SoC development. We often need to send a large amount of data from PL to PS for real-time processing, or send the processing results from PS to pl for real-time processing. In general, we will think of using DMA for processing, but various protocols are very troublesome and the flexibility is poor. This course explains how to use Axi directly Bus to read and write DDR data of PS terminal, which involves axi4 protocol, FPGA debugging of vivado, etc.)
- 2021-01-22 17:46:44下载
- 积分：1
