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float_int
自己编写的,浮点数与整数之间的转换的Verilog HDL实现(Written by myself, it is converted into Verilog HDL integer floating point implementation)
- 2020-12-18 10:29:11下载
- 积分:1
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FPGA
无线通信FPGA实现的代码 有matlab和verilog(FPGA implementation of wireless communication code matlab and verilog)
- 2012-09-17 10:39:40下载
- 积分:1
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Hardware Description Language VHDL of the frequency counter program can be used...
硬件描述语言VHDL的频率计程序,可用于做实验,或者初学者借鉴.-Hardware Description Language VHDL of the frequency counter program can be used for experiments, or the beginners learn.
- 2023-01-23 07:20:04下载
- 积分:1
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cpld/fpga common adder Verilog design procedures
cpld/fpga常用加法器设计的verilog程序-cpld/fpga common adder Verilog design procedures
- 2022-08-19 10:20:20下载
- 积分:1
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232543
FPGA Implementation of QFT based Controller for
a Buck type DC-DC Power Converter and
Comparison with Fractional and Integral Order PID
Controllers
- 2010-08-20 17:53:54下载
- 积分:1
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ps2接口源程序。标准的键盘和鼠标接口,在Xilinx SpartanII XC2S200 实验板上通过验证...
ps2接口源程序。标准的键盘和鼠标接口,在Xilinx SpartanII XC2S200 实验板上通过验证-ps2 interface source. Standard keyboard and mouse interface, in the experiments on-board Xilinx SpartanII XC2S200 validated
- 2023-03-24 22:15:03下载
- 积分:1
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gps
基于fpga和dsp架构的gps接收机的设计和实现(Design and Implementation of gps Receiver Based on fpga)
- 2017-05-25 17:44:51下载
- 积分:1
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完成十余卷积过程,简单方便,能够这样那样这样,sorry
完成十余卷积过程,简单方便,能够这样那样这样,sorry-Convolution process more than a decade to complete, simple and convenient, this can be done this way, sorry
- 2022-10-31 06:20:03下载
- 积分:1
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irda.tar
depends on irda transmitter recever
- 2009-11-20 00:31:48下载
- 积分:1
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对行为模型的全加器的VHDL代码
工具;
- 2022-04-18 04:42:27下载
- 积分:1