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Adder4
本设计是设计了一个4位全加器的内容,是由4个一位全加器串联而成的(The design is to design a full adder 4 content, is one of four full adder in series from the)
- 2009-05-11 19:50:58下载
- 积分:1
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总结设计中的重点及注意的地方,常出现错误的地方等。
总结设计中的重点及注意的地方,常出现错误的地方等。-Summarize the design of the focus and attention of local, often the wrong place and so on.
- 2022-08-24 04:12:36下载
- 积分:1
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alu3
用verilog语言编写,一个8-bit ALU,可以完成按字节的+、-和与、或、非操作(Using Verilog language, an 8-bit ALU, to be completed by byte+,- And, or, non-operating)
- 2008-05-12 12:48:49下载
- 积分:1
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计数器 0 到 9999
本程序显示在 BCD display 数从 0 到 9999.This 程序进行了智能 2 FPGA 板。
- 2022-05-08 02:50:35下载
- 积分:1
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jpeg_fpga
基于FPGA的JPEG解码,对开发图片解码的人有用。(FPGA-based JPEG decoding, the development of image decoding useful.)
- 2014-02-24 09:19:22下载
- 积分:1
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用verilog写的基于cpld的出租车计费器的源码,需要的参考一下
用verilog写的基于cpld的出租车计费器的源码,需要的参考一下-Use verilog to write a taxi based cpld billing device source code, need to refer to
- 2022-06-11 23:05:49下载
- 积分:1
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vhdl.9up
have a good documenty
- 2010-04-15 14:26:07下载
- 积分:1
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s3esk_cpld_design
Spartan-3E板卡XC2C64A CPLD 的代码(the XC2C64A CPLD on the Spartan-3E Starter Kit boards)
- 2009-12-01 00:40:17下载
- 积分:1
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VHDL版的C51核(MC8051)
VHDL版的C51核(MC8051)-VHDL version of the C51 core (MC8051)
- 2022-06-19 21:32:45下载
- 积分:1
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曼彻斯特编码技术用电压的变化表示0和1。规定在每个码元中间发生跳变。高→ 低的跳变表示0,低→ 高的跳变表示为1。每个码元中间都要发生跳变,接收端可将此变化提取...
曼彻斯特编码技术用电压的变化表示0和1。规定在每个码元中间发生跳变。高→ 低的跳变表示0,低→ 高的跳变表示为1。每个码元中间都要发生跳变,接收端可将此变化提取出来作为同步信号,使接收端的时钟与发送设备的时钟保持一致-Manchester coding techniques that use voltage changes in 0 and 1. Provisions in the middle of each symbol hopping happen. High → low hopping express 0, low → high jump for the express one. Symbol between each transition must happen, this change in the receiver can be extracted as a synchronization signal to the receiving end of the clock and send the equipment to maintain the same clock
- 2023-06-17 15:30:03下载
- 积分:1