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Matlab-and-Modelsim
matlab怎么把数据输入到modelsim，文件读写的问题(data write and read from matlab to modelsim)
- 2013-03-14 15:27:11下载
- 积分：1
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Altera Sdram IP 源码，VHDL写的
Altera Sdram IP 源码，VHDL写的-Altera Sdram IP source code, VHDL written
- 2022-04-21 21:08:22下载
- 积分：1
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ppm解码器
说明： 使用verilog实现ppm解码器，功能仿真通过，附设计说明，THU微纳电子系ic设计课大作业。(a ppm decoder written in VerilogHDL, a design document is available)
- 2020-11-26 20:09:31下载
- 积分：1
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half_band
半带滤波器verilog源代码，主要用于采样率变换系统中，采用乘法积累加器，很好的例子，供大家参考(Half band filter verilog code, mainly for the sampling rate conversion system, use the multiplication accumulation adder, a good example, for your reference)
- 2020-12-23 10:59:07下载
- 积分：1
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This code implements the output shift register functions, beginners can learn to...
本代码实现了输出移位寄存器功能，初学者可以借鉴学习-This code implements the output shift register functions, beginners can learn to learn
- 2022-06-20 09:32:02下载
- 积分：1
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移位寄存器。verilog VHDL
shift register. vhdl verilog
- 2023-06-29 10:50:03下载
- 积分：1
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hanming
用Verilog语言实现汉明编码，很粗燥，是大三的时候做的(With the Verilog language Hamming code, it is rough dry, a junior at the time to do)
- 2010-10-01 13:08:16下载
- 积分：1
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ag-overview
agilex fpga description
- 2019-05-13 18:21:04下载
- 积分：1
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divider
verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。(verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.)
- 2011-08-29 09:12:21下载
- 积分：1
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This program is Verlog language program, using QUARTUS6.0 preparation, program i...
本程序为Verlog语言程序，采用QUARTUS6.0编写，程序实现的功能是控制AD2S80的转换和和数据总线上数据的读取-This program is Verlog language program, using QUARTUS6.0 preparation, program implementation function is to control the conversion and AD2S80 and data bus to read data
- 2022-02-10 16:51:45下载
- 积分：1
