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xilinx_lib.tar
用于modelsim仿真的xilinxfpga平台IP库,以ise 13.x为基础制作,在modelsim10下验证通过。(xilinx IP core library for modelsim simulate, based on ise 13.x, verified in modelsim10.)
- 2017-10-27 12:23:53下载
- 积分:1
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DDS
文利用直接数字频率合成器(DDS)与CPLD技术和单片机控制技术,研制和
设计了高分辨率、高稳定度的函数信号发生(Wen using direct digital frequency synthesizer (DDS) and CPLD technology and single-chip microcomputer control technology, development and
Design of high resolution, high stability function of the signal
)
- 2013-08-27 14:20:22下载
- 积分:1
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16QAM-modulation-based-on-FPGA
基于FPGA的16QAM调制程序,基于verilog开发环境(16QAM modulation program based on FPGA-based development environment verilog)
- 2014-05-07 14:05:25下载
- 积分:1
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Designing Digital Down Conversion Systems with Altera CIC MegaCore and FIR Compe...
Designing Digital Down Conversion Systems with Altera CIC MegaCore and FIR Compensation Filter v6.1
- 2022-02-02 23:02:14下载
- 积分:1
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交通灯控制(VHDL)!!!!!!!!!!!!!!!!!!!!!!!!!!…
交通灯控制(VHDL)-Traffic Light Control (VHDL)! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
- 2023-03-20 10:30:04下载
- 积分:1
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EDA VHDL modules commonly used procedure, the time
EDA中常用模块VHDL程序,不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ,25分频=2HZ,10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)
- 2022-07-02 21:52:46下载
- 积分:1
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ORIGINAL_DOWNLOAD
说明: risc 8 by coonan compatible with PIC16C57
- 2019-12-05 20:32:55下载
- 积分:1
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m序列生成VHDL代码
伪随机m序列VHDL代码,生成多项式为1+x+x^7 (203),包括代码文件.vhd和模块文件.bsf以及仿真波形,可直接添加到工程中使用。
- 2023-02-01 13:50:03下载
- 积分:1
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Cirrus Logic EP9302 原理图 ORCAD格式
Cirrus Logic EP9302 原理图 ORCAD格式-Cirrus Logic EP9302 schematic ORCAD format
- 2022-08-22 05:47:43下载
- 积分:1
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UDP
用FPGA中的三速以太网来实现UDP通信,功能强大(With a triple-speed Ethernet in the FPGA to implement UDP communication, powerful)
- 2013-03-08 18:27:38下载
- 积分:1