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用 vhdl 语言实现Rs232
Altera DE2 上使用 vhdl 语言设计 RS232 控制器。这是一个串口模块可用于嵌入系统。
- 2022-03-09 23:32:48下载
- 积分:1
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I2S_2
that file is different I2S example
- 2014-11-27 06:39:52下载
- 积分:1
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MT9M001
FPGA驱动MT9M001的verilog代码,里面还有ddr3部分将图像数据进行存储,lcd进行图像显示,里面的摄像头驱动部分很详细,大家可以多研习研习(Verilog driver MT9M001 code, which is also the DDR3 image data storage, LCD display, which drives the part is very detailed, we can learn more)
- 2020-07-10 13:48:54下载
- 积分:1
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elevator
verilog语言写的一个四层电梯程序,有优先级的判断。(verilog language of a four-story elevator procedures to determine priority.)
- 2020-10-31 14:29:55下载
- 积分:1
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DS18B20的FPGA实现
基于FPGA的 温度传感器 DS18B20接口设计-FPGA DS18B20
- 2022-12-27 18:10:03下载
- 积分:1
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A4_Led3
led学习控制l44444444444444(led verilog led ccccccc)
- 2019-05-06 09:38:14下载
- 积分:1
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ldpc_decoder_802_3an
802.3an ldpc码编码、译码设计,使用VERILOG hdl语言编写,包括测试代码,(802.3an ldpc code encoding, decoding the design, use of language VERILOG hdl, including test code,)
- 2021-02-14 15:29:49下载
- 积分:1
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VERILOG HDL 实际工控项目源码
开发工具 altera quartus2
VERILOG HDL 实际工控项目源码
开发工具 altera quartus2-verilog HDL actual industrial projects source development tools altera quartus2
- 2022-02-07 05:53:32下载
- 积分:1
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3
说明: 利用vhdl语言编写的译码器程序,采用两种不同方式(The use of language decoder vhdl program, using two different ways)
- 2009-11-17 13:14:45下载
- 积分:1
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adc0809
1、用状态机设计A/D转换器ADC0809的采样控制电路,并在数码管上显示转换结果;
2、设置有复位和启动/保持开关,要求
⑴ 复位开关用来使A/D转换器复位,并做好A/D转换准备;
⑵ 启动/保持开关用来控制A/D转换器开始连续转换或停止转换保持结果,即按一下启动/保持开关,启动A/D转换器开始转换,再按一下启/停开关,停止转换并保持结果。
3、采用Verilog HDL语言设计符合上述功能要求的控制电路。(1, with the state machine design A/D converter ADC0809 sampling control circuit and display the results on the digital conversion 2 is provided with a reset and start/hold switch, reset switch is used to make the request ⑴ A/D converter reset and do A/D conversion ready ⑵ start/hold switch is used to control the A/D converter starts converting or stop the conversion to maintain a continuous result that by clicking Start/hold switch, start the A/D converter to start the conversion, and then Click the start/stop switch stops the conversion and keep the results. 3, using Verilog HDL language designed to meet the functional requirements of the above-mentioned control circuit.)
- 2021-01-02 21:38:57下载
- 积分:1