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TimeGen3
能够绘制数字电路的时序图,是fpga工程师时序设计和分析的神器(for digital circuit timming design and analysis)
- 2017-12-27 19:34:23下载
- 积分:1
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CME3000FPGADevelopment-
针对京微雅阁的CME300 FPGA教程,里面有几个例程,并附有源代码,初学者可尽快入门。(For Beijing micro Accord CME300 FPGA tutorial, there are a few routines, with source code, beginners can start as soon as possible.)
- 2013-08-19 18:01:21下载
- 积分:1
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EDA
说明: 十进制到十六进制转换的程序。程序要求从键盘取得一个十进制数,然后把该数以十六进制的形式在屏幕上显示出来。(Decimal to hex conversion program. Procedural requirements to obtain a decimal number from the keyboard, and then the hexadecimal number to be displayed on the screen.)
- 2011-03-27 16:42:04下载
- 积分:1
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用VHDL硬件描述语言实现的对FPGA(Cyclone II)的配置的VHDL源代码。...
用VHDL硬件描述语言实现的对FPGA(Cyclone II)的配置的VHDL源代码。-VHDL hardware description language for FPGA (Cyclone II) configurations VHDL source code.
- 2022-07-11 15:27:50下载
- 积分:1
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clk_generator
时钟分频代码,PWM产生 RTL 源代码。(clock divider,PWM generator RTL Source Code)
- 2013-08-18 09:29:42下载
- 积分:1
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Verilog entry basis, as well as introduce a simple programming, verilog in recen...
verilog入门基础以及简单编程介绍,verilog是近几年发展迅速的一门硬件语言-Verilog entry basis, as well as introduce a simple programming, verilog in recent years the rapid development of a hardware language
- 2023-01-25 17:05:04下载
- 积分:1
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Music_Player
这份代码完成的功能是通过蜂鸣器播放《梁祝》这首曲子,当然可以自行更改代码,以播放其它的乐曲,所用的硬件描述语言是VHDL,代码有四部分构成,顶层模块、预分频模块(产生基频)、音乐表格和分频模块(产生所需的各音调)。
- 2022-11-10 14:10:03下载
- 积分:1
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CORDIC算法的FFT实现
本代码实现了 ; ;CORDIC ; 算法语言;
- 2022-09-09 16:25:03下载
- 积分:1
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十六进制7Segment时钟
十六进制计数器递增 ALTERA FPGA 板 7 段显示器上的每一秒。
- 2022-07-13 21:46:37下载
- 积分:1
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alu
this file is vhdl code of alu
- 2016-05-29 16:35:58下载
- 积分:1