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4 位纹波计数器
用 vhdl 语言实现,上下计数器使用边缘触发一个 4 位纹波计数器。积极的边沿触发。
包含的所有文件。试验台架波形。针对采用赛灵思文件
- 2022-03-29 03:48:56下载
- 积分:1
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32FIRVHDL
基于FPGA的32阶FIR数字滤波器设计 源程序。设计使用了并行乘法器,运行速度更快,占用内存更小,延迟更小。
(32 order FIR digital filter based on FPGA design source program. Design USES parallel multiplier, faster and less memory, less delay.)
- 2014-05-12 21:11:19下载
- 积分:1
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LCD1602测试程序
实现对LCD1602的Verilog HDL编程(the program for LCD1602 based on Verilog HDL)
- 2020-06-23 21:00:01下载
- 积分:1
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周立公Verilog
关于verilog的知识点和关键点的总结(Summary of knowledge points and key points of Verilog)
- 2020-07-01 22:20:02下载
- 积分:1
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To increase simulation speed, ModelSim® can apply a variety of optimizations...
To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level of optimization by specifying certain switches when you invoke the compiler.
- 2022-03-06 09:05:21下载
- 积分:1
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license
quartus license dede(quartus 11.0 license)
- 2014-04-21 18:26:12下载
- 积分:1
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SDRAM基础性控制核 很有用的 VHDL状态机实现
SDRAM基础性控制核 很有用的 VHDL状态机实现-SDRAM control of the nuclear basic useful VHDL state machine implementation
- 2022-07-10 17:18:23下载
- 积分:1
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eDP
eDP接口TFT-LCD显示驱动原码(verilog+c)(eDP Interface TFT-LCD display driver source code (verilog+c))
- 2020-10-17 09:17:27下载
- 积分:1
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出租车记价器,使用vhdl语言编写的源码及其仿真。
出租车记价器,使用vhdl语言编写的源码及其仿真。-Taxi price of devices in mind, use the source code written in vhdl and simulation.
- 2022-03-06 03:11:59下载
- 积分:1
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project_first
说明: basys3的数字钟,可以显示00.00-59.59(Digital clock of basys3,It can display 00.00-59.59)
- 2019-06-18 10:37:53下载
- 积分:1