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costas
costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块(costas the verilog program, including multipliers, DDS, phase detector, loop filter modules)
- 2011-08-19 10:20:53下载
- 积分：1
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VHDL design entities, the basic structure of the language element of VHDL using...
VHDL设计实体的基本结构
VHDL的语言要素
用VHDL实现电路设计的方法
VHDL设计流程-VHDL design entities, the basic structure of the language element of VHDL using VHDL circuit design approach to achieve VHDL design flow
- 2022-08-10 09:13:22下载
- 积分：1
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arbiter_ip
Arbiter code for simulation purpose
- 2013-07-13 17:45:11下载
- 积分：1
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Tri-Eth
采用xilinx三太以太网ip核，tri-mode MAC完成千兆以太网数据传输(Too Ethernet using xilinx ip three nuclear, tri-mode MAC Gigabit Ethernet data transmission is completed)
- 2014-03-06 22:00:43下载
- 积分：1
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电梯
利用verilog编写的电梯程序，实现基本的电梯运行功能(Elevator program written by Verilog)
- 2018-11-25 11:39:50下载
- 积分：1
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mealy_sequence
实现米粒状态机
用verilog语言实现状态机的过程(Implement a state machine with a grain of rice verilog state machine language course)
- 2011-11-09 19:02:27下载
- 积分：1
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zongbian4
基于verilog语言的差分曼彻斯特编码，内包含数据的采集，CRC校验（8位），和编码，输出。附有完整的工程文件。可直接调用modelsim仿真。(Based on differential Manchester encoding verilog language, and contains data collection, CRC check (8), and coding. With complete project file. Modelsim simulation can be called directly.)
- 2021-03-04 09:59:32下载
- 积分：1
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thesis
thesis for simple virus detection processor which is developed in xilinx
- 2015-02-18 23:51:11下载
- 积分：1
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VerilogHDL.自动增益控制模块中产生控制电压的部分
VerilogHDL.自动增益控制模块中产生控制电压的部分-VerilogHDL. Automatic Gain Control Module have some control voltage
- 2022-06-19 20:17:38下载
- 积分：1
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sample_wave
可以产生8比特的采样波形，非常不错的VHDL程序(Sampling can produce 8-bit waveform, very good VHDL program)
- 2010-10-12 20:03:07下载
- 积分：1
