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application vhdl language adder design, compared with the design, With vhdl lang...
应用vhdl语言进行加法器的设计，比较器的设计，随着vhdl语言的应用越来越广泛，其重要性也更加明确。希望对大家有所帮助。-application vhdl language adder design, compared with the design, With vhdl language widely used, the importance of which was more explicit. We want to help.
- 2022-04-16 15:59:21下载
- 积分：1
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fsk
基于FPGA的fsk调制程序，包括载波的生成，nco的设置(FPGA-based fsk modulation procedures, including carrier generation, nco settings)
- 2016-05-12 21:00:56下载
- 积分：1
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HDB3 ENCODING AND DECODING METHOD
HDB3 ENCODING AND DECODING METHOD
- 2022-12-23 08:30:03下载
- 积分：1
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一个16位cpu的vhdl代码。具体内容我也不清楚，自己慢慢研究吧...
一个16位cpu的vhdl代码。具体内容我也不清楚，自己慢慢研究吧-a 16 cpu of VHDL code. Specific content is not clear to me that their study it slowly
- 2022-01-26 05:10:10下载
- 积分：1
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一个霹雳灯的Verilog源程序，用PWM原理实现，产生了LED灯的渐弱效果...
一个霹雳灯的Verilog源程序，用PWM原理实现，产生了LED灯的渐弱效果-a thunderbolt lights Verilog source files, using PWM principle realized, LED lights have a gradual effect of the weak
- 2023-07-28 11:50:03下载
- 积分：1
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SoC_WishboneSystem
SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。(SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)
- 2008-01-03 11:14:59下载
- 积分：1
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can总线
说明： SJA1000的ip核和相关测试脚本,OPENCORES 下载(SJA1000 IP downloads from opencores)
- 2019-11-15 10:07:14下载
- 积分：1
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zixiechengxu
用verilog编写的包含有与DSP通信，三电平svpwm实现的程序，(Written in verilog contains communicate with the DSP, three-level svpwm realize the procedures)
- 2021-04-18 15:28:51下载
- 积分：1
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src
假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 + 寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)
- 2020-12-15 13:49:14下载
- 积分：1
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ug848-VC707-getting-started-guide
vc707 board getting started guide
- 2018-06-14 05:52:39下载
- 积分：1
