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test bench for alu 6 functions

于 2022-03-02 发布 文件大小:880.00 B
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test bench for alu 6 functions

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  • 此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块,一个提供同步信号(H_SYNC和V_SYNC)及像素位置信息;...
    此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块,一个提供同步信号(H_SYNC和V_SYNC)及像素位置信息;另一个接收像素位置信息,并输出颜色信号。这样便于进行图形修改,同时也容易实现- This design uses Verilog the HDL hardware language design, realizes on the palm space development board Divides into two stature modules the entire electric circuit, provides the synchronized signal (H_SYNC and V_SYNC) and the picture element positional information; Another receive picture element positional information, and output color signal. Like this is advantageous for carries on the graph to revise, simultaneously is also easy to realize
    2022-04-07 13:58:38下载
    积分:1
  • 该源码为VHDL语言编写的分频器,在W
    该源码为VHDL语言编写的分频器,在W-4b教学平台上通过验证-The VHDL source for the prescaler languages, W-4b in the teaching platform validated
    2022-01-24 14:12:26下载
    积分:1
  • 测试人体视觉的反应时间,可以作为vhdl编程的练习之用,也可以更进一步的开发成为具有商业价值的产品,这里面只是能够实现测试人体视觉反应时间的基本功能的程序...
    测试人体视觉的反应时间,可以作为vhdl编程的练习之用,也可以更进一步的开发成为具有商业价值的产品,这里面只是能够实现测试人体视觉反应时间的基本功能的程序-Test of human visual reaction time, can be used as VHDL programming exercises used can also be further developed into products with commercial value, there is only able to realize the human visual reaction time test the basic functions of the procedures
    2022-10-07 16:40:02下载
    积分:1
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    用FPGA实现OFDM系统,硬件语言为Verilog,环境为xilinx,详细介绍了接收机和发射机各个模块的源代码(OFDM system with a FPGA implementation, hardware language Verilog, environment xilinx, details of receiver and transmitter modules source code)
    2015-05-11 08:58:13下载
    积分:1
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    2010-11-13 23:31:11下载
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