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FPGA 累加器
该项目是在的Quartus2实施,Altera公司的在DE2开发板....
设计有一个功能来积累给定的输出...这必须学习在Verilog HDL语言的基本编码..
这仍是如此基本的编程,它必须加强和改进..
使它成为一个更复杂的UT还精确的编码方案...谢谢你看我的工作..
- 2022-06-20 14:39:07下载
- 积分:1
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thesis
thesis for simple virus detection processor which is developed in xilinx
- 2015-02-18 23:51:11下载
- 积分:1
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QC_LDPC_FPGA
LDPC QC-LDPC 基于FPGA的QC-LDPC实现 论文(LDPC QC-LDPC FPGA-based QC-LDPC detailed implementation steps
Thesis)
- 2021-04-08 09:29:00下载
- 积分:1
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ASKMod
ASK调制信号的verilog VHL设计,在ise中实现了ASK信号的调制解调。(ASK modulation signal verilog VHL design, in ise to achieve the ASK signal modulation and demodulation.)
- 2017-04-17 10:46:19下载
- 积分:1
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Tempe_deteV2.1
说明: FPGA接收串口UART发来的指令设定温度报警值,实时采集DS18B20温度传感器并显示,带报警功能(FPGA receives the instruction from UART, sets the temperature alarm value, collects and displays DS18B20 temperature sensor in real time, with alarm function)
- 2021-04-13 13:28:56下载
- 积分:1
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Four-controllable-counter
说明: 功能是(用Verilog语言的,内有比较详细的注释):
(1)计数器的功能是从0到9999计数,并能以十进制数的形式在七段数码管上显示出来(包括七段数码管显示模块).
(2)该计数器有一个1个nclr和一个adj_plus端,在控制信号的作用下(见下表),计数器具有复位、增或减计数、暂停的功能。编写以上的程序的完整模块.
计数器的功能表
nclr adj_minus 功 能
0 0 复位为0
0 1 递增计数
1 0 递减计数
1 1 暂停计数
(Function is (with Verilog language, the more detailed comments): (1) counter function is from 0 to 9999 counts, and are able to form a decimal number on the seven-segment LED display (including the seven-segment LED display module). (2) The counter has a one nclr and a adj_plus side, under the action of the control signal (see below), the counter has reset, increase or decrease of count pause function. Complete the preparation of the above program modules. Counter function menu nclr adj_minus reset 0 0 0 0 1 1 0 counts counting suspended Count 1 1)
- 2011-03-01 22:47:51下载
- 积分:1
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hdl_adder
说明: MATLAB to HDL Code conversion
- 2020-06-17 12:40:01下载
- 积分:1
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一个I2C从机代码
I2C从机代码,按照I2C基本协议用verilog语言编写,包含了测试模块,建议用xilinx设计套件,加载代码和测试。
- 2022-03-05 23:23:57下载
- 积分:1
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9536
Xilinx user constraints file for the cpld xc9536 or xc9536xl or xc9572 or xc9572xl
- 2012-11-06 11:49:12下载
- 积分:1
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jjj
实现了四bit计数器的功能,使用的是VHDL语言描述(Four-bit counter, using the VHDL language description)
- 2012-12-20 10:53:46下载
- 积分:1