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half_band
半带滤波器verilog源代码，主要用于采样率变换系统中，采用乘法积累加器，很好的例子，供大家参考(Half band filter verilog code, mainly for the sampling rate conversion system, use the multiplication accumulation adder, a good example, for your reference)
- 2020-12-23 10:59:07下载
- 积分：1
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practical_lift_controller
实用电梯控制器
实用电梯控制系统block symbol file
实用电梯控制器的Verilo
practical_lift_controller
实用电梯控制器
实用电梯控制系统block symbol file
实用电梯控制器的Verilog HDL程设计-practical utility practical_lift_controller elevator controller elevator control system block symbol file utility elevator controller Verilog HDL-way design
- 2023-03-27 22:00:04下载
- 积分：1
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src
yuv444 与yuv422相互转换verilog语言(yuv444 to yuv422)
- 2021-01-20 14:38:41下载
- 积分：1
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VHDL Digital Full ADDER Logic Program
- 2022-08-03 08:35:11下载
- 积分：1
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rotary
Spartan 3E上的Rotary encoder控制程序，及验证它的小灯程序(Rotary encoder on the Spartan 3E control procedures, and verification procedures for its small light)
- 2010-11-27 01:40:13下载
- 积分：1
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acx735_usb_ddr3_tft
说明： USB传图至fpga板缓存至DDR内，FPGA再读出图像数据，显示在TFT彩屏上；(USB to the FPGA board cache DDR, FPGA read out the image data, display on the TFT color screen;)
- 2021-01-30 18:06:45下载
- 积分：1
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基于vhdl的PWM发生器
基于vhdl的PWM发生器-VHDL-based PWM generator
- 2022-03-04 15:27:12下载
- 积分：1
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人脸识别（3D）
说明： 基于高清视频的3D人脸识别源代码，四万多行，经过FPGA实际验证，最近调试完毕。(The source code of 3D face recognition based on HD video, more than 40,000 lines, has been verified by the actual FPGA, and has been debugged recently.)
- 2019-07-01 16:22:46下载
- 积分：1
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M_M
此为数学形态滤波器消燥的代码，用于一维信号，涉及一个具体的例子，需要的话可以自己修改，修改相应的结构元素。(This is a mathematical morphology filter away dry code, used to one dimensional signal, involving a concrete example, necessary can change ourselves, change the structure of the corresponding elements)
- 2013-08-29 21:36:37下载
- 积分：1
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full adder in vhdl of 4 bits
full adder in vhdl of 4 bits
- 2022-02-01 04:44:39下载
- 积分：1
