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MPSK-modulation-and-demodulati
MPSK调制与解调VHDL程序源代码与仿真(MPSK modulation and demodulation process and VHDL source code and simulation)
- 2014-02-28 15:23:56下载
- 积分：1
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Altera FPGA IP core of the source code for the use of Altera FPGA design to prov...
ALTERA的FPGA的IP核的源代码,为使用ALTERA的FPGA的相关设计提供参考.-Altera FPGA IP core of the source code for the use of Altera FPGA design to provide the relevant information.
- 2022-04-30 06:15:53下载
- 积分：1
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electricwatch
用VHDL语言设计多功能的电子表。实现基本电子表的时间显示、闹钟、秒表等功能(VHDL language design with multi-functional electronic watch. The time table to achieve basic electronic display, alarm clock, stopwatch functions)
- 2010-05-07 17:11:53下载
- 积分：1
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clk_div_4
说明： Verilog代码实现四分屏，在Vivado平台下实现的，可仿真(Verilog code realizes four screens, which can be simulated under vivado platform)
- 2020-12-21 20:39:08下载
- 积分：1
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HDB3
FPGA实验_HDB3编码器设计(包含5个模块)(FPGA design experiments _HDB3 encoder (including 5 modules))
- 2020-11-30 10:29:28下载
- 积分：1
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DDS_BPSK
基于DDS的BPSK调制器设计Verilog源码( U57FA u4E8.08 u868)
- 2017-04-28 11:44:46下载
- 积分：1
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对NC Verilog的基本介绍，详细的图解，非常适合初学者使用，一个word文档和一个pdf文档...
对NC Verilog的基本介绍，详细的图解，非常适合初学者使用，一个word文档和一个pdf文档-NC Verilog on the basic introduction, detailed diagrams, very suitable for beginners to use, a word document and a pdf document
- 2022-08-12 19:52:59下载
- 积分：1
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键盘扫描，实现4×4键盘扫描功能，实现在数码管上显示相应的数字...
键盘扫描，实现4×4键盘扫描功能，实现在数码管上显示相应的数字-Keyboard scanning, the realization of 4 × 4 keyboard scan function, the realization of digital tube display in the corresponding figure
- 2022-02-06 05:08:26下载
- 积分：1
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24x24-booth
可用的24位x24位的booth乘法器的verilog代码(24X24 booth muplily)
- 2011-06-09 17:59:26下载
- 积分：1
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FPGA realization of DDS with the schematic diagram, structural clarity, the use...
用FPGA实现DDS的原理图，结构清晰，采用总线方式与外部单片机通信-FPGA realization of DDS with the schematic diagram, structural clarity, the use of bus-way communication with the outside Singlechip
- 2022-04-16 10:26:17下载
- 积分：1
