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24小时计时时钟
说明： 实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)
- 2020-06-23 19:40:01下载
- 积分：1
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hard work for Dictyophora development. . We hope that the right useful.
辛辛苦苦的作品应用于DE2 的 开发。。希望对大家有用。-hard work for Dictyophora development. . We hope that the right useful.
- 2022-05-25 11:15:19下载
- 积分：1
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CH4CH2CH1VHDL 数字电路参考书所有程序9
CH4CH2CH1VHDL 数字电路参考书所有程序9-CH4CH2CH1VHDL digital circuit reference all proceedings 9
- 2022-11-24 11:15:04下载
- 积分：1
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在Quartus环境中，采用VHDL语言编写的出租车计费系统，系统共分为分频、状态切换、记程、计费等模块，模仿现实中出租车计费。...
在Quartus环境中，采用VHDL语言编写的出租车计费系统，系统共分为分频、状态切换、记程、计费等模块，模仿现实中出租车计费。-In the Quartus environment, the use of VHDL language taxi billing system, the system is divided into sub-frequency, state switching, recording process, billing and other modules, to imitate reality, taxi billing.
- 2022-02-25 18:59:33下载
- 积分：1
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multiplier
参数可配置的sequential 乘法器和booth 乘法器(verilog source code with configurable parameters for sequential multiplier and booth multiplier )
- 2011-12-08 15:14:04下载
- 积分：1
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NIOS II based on the SD CARD MUSIC PLAYER source, including hardware SOPC
基于NIOS II的SD CARD MUSIC PLAYER源码，包括硬件SOPC-NIOS II based on the SD CARD MUSIC PLAYER source, including hardware SOPC
- 2023-02-13 09:35:05下载
- 积分：1
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QAM_verilog
基于FPGA的16QAM，用verilog编写，其中DDS为自己编写，含设计文件和testbench。已通过moldesim软件仿真。 (FPGA-based 16QAM, with verilog writing, including DDS for their preparation, including design files and testbench. Simulation software has been through moldesim.)
- 2021-02-22 18:29:41下载
- 积分：1
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VGA_test
vga很好的学习材料，测试程序，欢迎下载(vga good learning materials, testing procedures, please download)
- 2010-08-17 22:32:45下载
- 积分：1
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classdiagramnew
class diagram diagram for AIRS
- 2015-06-10 22:44:10下载
- 积分：1
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DDS_signal_genarator
这是一个利用verilog语言编写的信号发生器的例子，值得参考(this is a code about signal generator by VIERILOG LANGUAGE!)
- 2013-12-23 10:12:52下载
- 积分：1
