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BIT
说明： FPGA应用状态机版，适合初学者学习状态机三段式，ASMD图的理解和翻译，以及Verilog语言的应用 最后对仿真的一些理解 其中包含HDL设计及testbench描述
根据要求设计了一个能求出一个32bit字中两个相邻0之间最大间隙的电路。(FPGA application state machine version, suitable for beginners to learn state machine three-stage, ASMD chart understanding and translation, and Verilog language application. Finally, some understanding of simulation, including HDL design and testbench description
According to the requirements, a circuit is designed to find the maximum gap between two adjacent zeros in a 32 bit word.)
- 2020-04-28 15:57:34下载
- 积分：1
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mmuart
说明： 简单uart，verilog语言编写，已经经过测试，有需要的可以看看(Simple uart, Verilog language, has been tested, you can see if you need it)
- 2020-06-23 20:00:01下载
- 积分：1
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music
说明： 是用VHDL语言编写的乐曲演奏程序，详细的写了各个模块的子程序(VHDL language is the music playing program)
- 2009-08-17 08:52:31下载
- 积分：1
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本文件解压后clock_time.vhd采用编程环境maxplusII，完成时间秒定时、记时，设置时间秒、声光报警等功能。...
本文件解压后clock_time.vhd采用编程环境maxplusII，完成时间秒定时、记时，设置时间秒、声光报警等功能。-this document unpacked clock_time.vhd maxplusII use programming environment, the time for completion seconds timing, Hutchison, the set-up time seconds, sound, light, alarm functions.
- 2022-07-03 03:02:23下载
- 积分：1
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medianfilter
图像滤波中的中值滤波，有效滤除椒盐噪声，使用verilog语言编写(Image filtering in the median filter, effectively filter out salt and pepper noise, using verilog language)
- 2011-10-13 17:08:48下载
- 积分：1
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Timing_Closure
详细讲解时序约束培训教材，有利于更好对时序约束的理解(Timing constraints elaborate training materials, facilitate better understanding of the timing constraints)
- 2010-08-12 20:02:33下载
- 积分：1
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ofdm_cp_insertion
ofdm_cp_insertion add/remove CP
- 2015-01-29 21:25:47下载
- 积分：1
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使用VHDL语言编程，烧录在芯片运行的倒数5秒响4声短铃最后一声长音的数字钟...
使用VHDL语言编程，烧录在芯片运行的倒数5秒响4声短铃最后一声长音的数字钟-The use of VHDL language programming, burn in the chip to run the last 5 seconds short bell ring 4 final say sound a long tone of digital clock
- 2022-06-20 16:23:08下载
- 积分：1
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8位相等比较器，比较8位数是否相等
8位相等比较器，比较8位数是否相等
-- 8-bit Identity Comparator
-- uses 1993 std VHDL
-- download from www.pld.com.cn & www.fpga.com.cn-eight other phase comparators, Comparing the same whether the median 8-- 8-bit Identity Comparator-- uses 1993 std VHDL-- download from www.pld.com.cn
- 2022-06-21 10:57:15下载
- 积分：1
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1_Carm
说明： 经典的OV5642的verilog驱动程序(Verilog Driver of Classic OV5642)
- 2019-03-19 13:38:29下载
- 积分：1
