登录
首页 » VHDL » Elevator designed to control the lift design 6 original VHDL language

Elevator designed to control the lift design 6 original VHDL language

于 2022-02-06 发布 文件大小:158.92 kB
0 135
下载积分: 2 下载次数: 2

代码说明:

电梯的设计・用来控制6层的电梯设计原来・VHDL语言-Elevator designed to control the lift design 6 original VHDL language

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 一种基于LUT的预失真方法。其中的一部分,有参考价值。
    一种基于LUT的预失真方法。其中的一部分,有参考价值。-one method of DPD based on LUT
    2022-06-30 17:35:36下载
    积分:1
  • Farrow-filter-design
    两篇中文论文,详细叙述了Farrow滤波器的设计方式和理论基础,非常实用!(Two Chinese papers, described in detail Farrow filter design methods and theoretical foundation, very useful!)
    2013-11-15 17:15:20下载
    积分:1
  • 24小时时钟设计程序,含有时,分,秒的电路设计,基于VHDL语言,用Quartus 2程序实现。...
    24小时时钟设计程序,含有时,分,秒的电路设计,基于VHDL语言,用Quartus 2程序实现。-24-hour clock design process, with hour, minute, second circuit design, based on the VHDL language, using Quartus 2 program.
    2022-03-23 02:16:08下载
    积分:1
  • 电子时钟
    基于DE2-115的数字时钟 1.液晶显示,数码管显示 2.整点报时 3.闹钟 4.设置时间 5.设置闹钟(Digital clock based on DE2-115 1. LCD display, digital tube display 2. whole point 3. alarm clock 4. setting time 5. set the alarm clock)
    2021-03-06 23:39:29下载
    积分:1
  • SPI接口的实现以及对外设的读写操作,其中包扩了几种工作方式,同时可以读取外设的版本号,传输速率可以达到2Mbps...
    SPI接口的实现以及对外设的读写操作,其中包扩了几种工作方式,同时可以读取外设的版本号,传输速率可以达到2Mbps-SPI interface implementation, as well as read and write operations on the peripheral, which extended several work packages at the same time can read the version number of peripherals, transfer rate up to 2Mbps
    2022-03-19 12:53:00下载
    积分:1
  • 基于FPGA的VGA彩条显示 可用PAXplusII仿真
    基于FPGA的VGA彩条显示 可用PAXplusII仿真-FPGA-based VGA color display available PAXplusII Simulation of
    2022-07-12 22:45:31下载
    积分:1
  • SimpleSpi
    master spi的源代码(verilog),包括文档,测试程序(master spi the source code (verilog), including documentation, testing procedures)
    2007-01-29 21:03:51下载
    积分:1
  • MemoryGame-master
    在开发板EGO1上实现的图形记忆游戏,白块按下确认建,黑色块不按确认键(memory game in verilog)
    2020-12-19 16:29:10下载
    积分:1
  • DDC_Ver1.0
    数字下变频(DDC)在如今基于软件无线电的架构中对系统的整体性能决定性的影响,代码为基于Matlab的4通道DDC程序,程序中可以根据需要调节滤波器等参数评估DDC的性能对于使用FPGA实现DDC有较大的参考价值(Digital down conversion (DDC) in today' s architecture based on software radio system a decisive impact on the overall performance of the code for the 4-channel DDC Matlab-based program, the program can be adjusted according to filter parameters such as the use of performance assessment FPGA DDC DDC has achieved great reference value)
    2010-08-04 18:33:14下载
    积分:1
  • FFT_64points
    64点的 FFT verilog,它是串行计算的,工作频率不到100M,计算速率很高,里面的层次很清晰。(64-point FFT verilog serial computing, the operating frequency of less than 100M, the calculated rate is high, the level inside is very clear.)
    2021-04-03 11:29:07下载
    积分:1
  • 696518资源总数
  • 106164会员总数
  • 18今日下载