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jishi
计时器=================(Timer =================)
- 2009-12-27 21:41:10下载
- 积分：1
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alu
verilog code for 8 bit alu
- 2015-06-30 18:49:10下载
- 积分：1
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smartWasher
QUARTER编程环境实现的智能洗衣机系统，通过DE0板子进行模拟，组要完成洗衣机5个步骤的顺序过程以及系统相应动作(QUARTER programming environment of intelligent washing system, through simulation DE0 board, groups 5 to complete the washing process and the system the sequence of steps corresponding action)
- 2020-11-06 13:19:49下载
- 积分：1
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CJ2
关键词：清华大学计算机系 计算机组成原理大实验 多周期cpu工程源码，内含中断，串口，以及31个指令的实现，读写内存，控制器，ALU，寄存器，分频等模块，小作业什么的可以直接从里面摘抄，为学弟学妹造福(Keywords: Department of Computer Science Computer Composition Principle experimental multi-cycle the cpu Engineering source for the benefit of mentees)
- 2020-12-29 10:09:01下载
- 积分：1
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dct_verilog
用FPGA实现dct变换。verilog语言实现，在quartus9.0中验证，含整个工程(dct transform verilog language in quartus9.0 verify, with the entire project)
- 2020-12-02 18:59:24下载
- 积分：1
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SRIO-phy-code
SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考(SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development)
- 2020-10-01 11:57:42下载
- 积分：1
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用VHDL实现的DDS逻辑，大家可以参考下
用VHDL实现的DDS逻辑，大家可以参考下-DDS achieved using VHDL logic, we can refer to the following
- 2022-08-10 09:43:58下载
- 积分：1
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用vhdl描写的通用异步改进dram控制器，经过编译器综合和仿真测试，符合设计要求。...
用vhdl描写的通用异步改进dram控制器，经过编译器综合和仿真测试，符合设计要求。-Using VHDL description Universal Asynchronous improved dram controller, through an integrated compiler and simulation testing, in line with the design requirements.
- 2022-04-19 09:59:57下载
- 积分：1
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detection of the following sequence ‘10110110’in VHDL
detection of the following sequence ‘10110110’in VHDL
- 2023-04-17 19:05:03下载
- 积分：1
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full adder设计代码，verilog 语言描述，通过modelsim 仿真，quartus综合...
full adder设计代码，verilog 语言描述，通过modelsim 仿真，quartus综合-full adder design code, verilog language to describe, through the ModelSim simulation, quartus integrated
- 2022-06-30 03:26:15下载
- 积分：1
