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Kay_algorithm
QPSK调制的载波频偏估计，是一个可以调用的函数。接收端进行了一系列的处理。经典的Kay法(QPSK-carrier frequence offset estimation_ kay )
- 2013-03-18 14:36:29下载
- 积分：1
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mux8to1_with_if
this code to input 8 different data and make them out sequentialy
- 2015-02-19 10:54:20下载
- 积分：1
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maichongceliang
对于已获得的脉冲包络采样序列，需测量的脉冲特征参数主要有：脉冲幅值(PA)、脉冲到达时间(TOA)和脉冲宽度(PW)。实际测量中，脉冲波形的形状是各种各样的，但其主要的参数有脉冲幅度、脉冲宽度、脉冲周期、脉冲占空比、脉冲前沿(上升时间)、脉冲后沿(下降时间)、脉冲上冲、脉冲下冲、脉冲下垂、脉冲顶部不平度等，脉冲参数的计量主要就是对这些参数进行计量。本程序包实现基于FPGA实现脉冲宽度和重复周期的测量。(Who have access to the pulse envelope sample sequence, the pulse measurement to be the main characteristic parameters are: pulse amplitude (PA), pulse time of arrival (TOA) and pulse width (PW). The actual measurement, the pulse shape is a wide variety of shapes, but its main parameters of the pulse amplitude, pulse width, pulse period, pulse duty cycle, pulse leading edge (rise time), pulse along (down time), the red pulse, pulse undershoot, pulse droop, pulse irregularities, such as at the top, the measurement of pulse parameters is mainly the measurement of these parameters. The package FPGA-based pulse width and repetition to achieve the measurement cycle.)
- 2009-07-08 14:32:08下载
- 积分：1
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明白4
实现了一个四层单电梯控制系统。门可以自动开关，也可以手动开关。代码可以集成，不超过驱动的现象。
- 2022-04-10 00:20:47下载
- 积分：1
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design-of-CAN-based-on-VHDL
基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性(Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the CAN bus communication controller front-end design. Verilog HDL language that is used to complete the data link layer CAN protocol the RTL-level design, to achieve its function, and can be on the FPGA development platform Quartos by simulation to prove its correctness)
- 2011-07-22 15:22:27下载
- 积分：1
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一个模拟ISA界面的简易小程式，简单易懂
一个模拟ISA界面的简易小程式，简单易懂-ISA interface, a simple simulation of a small program, easy-to-read
- 2022-07-24 01:55:08下载
- 积分：1
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ldpc_decoder_802_3an
LDPC的编码模块和解码模块，实现802-3an协议的编码(The module of LDPC to implement the coding of the 802-3an protocol)
- 2018-07-23 15:01:20下载
- 积分：1
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这是一个用VHDL语言描述的I2C自动配置模块，使用了来自opencores.org的I2C核，已在altera的cyclone芯片上调试通过...
这是一个用VHDL语言描述的I2C自动配置模块，使用了来自opencores.org的I2C核，已在altera的cyclone芯片上调试通过-This is a VHDL language used to describe auto-configuration of the I2C module, the use of the I2C from opencores.org nucleus, the cyclone in the altera-chip debugging through
- 2022-07-13 04:31:50下载
- 积分：1
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PulseWidth_detector_VHDL
通信控制中常用的脉冲宽度检测程序，VHDL模块化编成实现（原创）(communication control used in pulse width detection procedures, VHDL modular organization to achieve (original))
- 2007-03-28 17:41:46下载
- 积分：1
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rtl_wangjiangxing
ecc椭圆算法RTL,verilog源代码经过验证，用于FPGA或者ASIC(ECC elliptic curve encryption algorithm for Verilog implementation)
- 2015-01-29 18:43:47下载
- 积分：1
