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FDDDDRSDRAMP
一种基于FPGA 实现DDDR SDRAM的控制器
(DDDR SDRAM controller based on FPGA)
- 2012-08-29 23:52:53下载
- 积分：1
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pipeline_booth_mult_16
用流水线的方法实现16位乘法器，运算速度快，消耗时钟资源少(Pipeline method to realize 16-bit multiplier, which is fast in operation and consumes less clock resources)
- 2020-09-29 18:17:44下载
- 积分：1
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LED 闪烁的VHDL代码
LED闪烁的VHDL代码
- 2022-07-28 10:23:55下载
- 积分：1
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Design-Compiler-Reference
dc的应用规范，以及一些基础的操作指导，注意事项等(dc application specification, as well as some basic instructions, precautions, etc.)
- 2013-08-13 11:14:47下载
- 积分：1
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CRC-Verilog
此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16(this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY)
- 2007-01-03 10:47:43下载
- 积分：1
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是使用VHDL语言编写的基于FPGA的uart的源代码！
是使用VHDL语言编写的基于FPGA的uart的源代码！-VHDL language is to use FPGA-based uart source code!
- 2022-07-10 13:34:40下载
- 积分：1
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一些有用的PicoBlaze的来源。
Some useful PicoBlaze sources.
- 2022-01-26 02:08:20下载
- 积分：1
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程序是用硬件描述语言（VHDL）实现：4×4键…
程序主要是用硬件描述语言（VHDL）实现：
4*4键盘扫描，简洁明了，通俗易懂，比较适合VHDL初学者-procedure was used in hardware description language (VHDL) to achieve : 4* 4 keyboard scan, concise, easily understood and more suitable for beginners VHDL
- 2022-01-31 18:02:15下载
- 积分：1
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veye_mipi
说明： 1、 例程功能VEYE-290-LVDS模组视频接入演示。（显示设备必须支持1080p/30或1080p/25的帧率）
Veye模组—>MIA701开发板—>HDMI显示设备
2、 本例程硬件平台
MIA701-PCIE开发板，FPGA芯片：XC7A100TFGG484
3、 软件平台Vivado2018.1。
4、 附件含开发板原理图（底板+核心板）(1. Video access demonstration of routine function VEYE-290-LVDS module. (Display devices must support 1080p/30 or 1080p/25 frame rates) Veye Module - > MIA701 Development Board - > HDMI Display Equipment 2. The hardware platform of this routine MIA701-PCIE development board, FPGA chip: XC7A100TFG484 3. Software platform Vivado 2018.1. 4. Appendix contains schematic diagram of development board (bottom + core board))
- 2019-04-01 11:08:04下载
- 积分：1
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FPGA
fpga 设计全攻略，很好的fpga入门提高资料(the fpga design Raiders, good fpga the Getting Started improve data)
- 2012-12-09 19:03:23下载
- 积分：1
