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static-timing-analyze
特权同学主讲的FPGA设计的时序约束专题（STA部分）(Speaker privileged classmates timing constraints for FPGA design topics (STA section))
- 2013-07-11 13:23:46下载
- 积分：1
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MD5
哈希算法FPGA实现代码，采用MD5算法，并给出了仿真波形。(MD5 hashing algorithm for FPGA implementation code)
- 2020-07-03 00:40:02下载
- 积分：1
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S3EStarter_user-guide
Xilinx Spartan-3E Starter Kit Board User Guide(中文用户手册)(Xilinx Spartan-3E Starter Kit Board User Guide)
- 2012-04-30 10:14:18下载
- 积分：1
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rmii
rmii 以太网接口时序源代码，值得开发借鉴的哦(verilog hdl)
- 2013-10-12 09:56:24下载
- 积分：1
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7-segment
一个7段的显示器，及按一定顺序循环得到的结果，可重复使用(A 7-segment display, and by a certain sequence and cycle the results obtained can be reused)
- 2010-01-10 18:21:33下载
- 积分：1
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SSI-ABZ
SSI转ABZ信号FPGA程序，测试完全可用(Function of SSI convert to ABZ signal,is available)
- 2019-05-19 15:37:48下载
- 积分：1
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VHDL-Handbook.pdf
VHDL Handbook by HARDI Electronics AB
- 2015-02-17 17:50:32下载
- 积分：1
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61EDA_C2212
红色飓风II开发板USB2FPGA USB驱动程序，由verilog编写，包括源码和FIFO测试程序(Red Hurricane II development board USB2FPGA USB driver from verilog preparation, including source code and test procedures FIFO)
- 2013-05-30 14:22:07下载
- 积分：1
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分数时延FIR
说明： 分数时延FIR滤波器FPGA设计的相关资料及软件无线电实验平台MFSS6842使用说明(Fractional delay FIR filter FPGA design related information and software radio experimental platform MFSS6842 instructions)
- 2019-11-18 22:45:35下载
- 积分：1
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gwnseq
verilog产生高斯白噪声，gwn_en信号产生使能，gdata是幅度服从高斯分布，功率谱密度为定值的高斯白噪声序列，共10位（现实中只能够做到带限，跟dac输出带宽有关，我的系统只能做到300kHz）(verilog Gaussian white noise, gwn_en signal enabled, gdata amplitude Gaussian distribution, power spectral density of white Gaussian noise sequence value, a total of 10 (in reality can only be band-limited, with dac output bandwidth related, My system can do 300kHz))
- 2014-06-13 13:18:45下载
- 积分：1
