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simpleCpu
relative cpu design implementation
- 2013-08-14 21:22:39下载
- 积分：1
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256M_sdram_OK
改自特权同学verilog语言写sdram测试程序；支持256M内存(verilog sdram )
- 2013-12-23 16:15:43下载
- 积分：1
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File name: ADC0809.vhd features: Based on the VHDL language, easy to control imp...
文件名：ADC0809.vhd功能：基于VHDL语言，实现对ADC0809简单控制说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Description: ADC0809 internal clock does not need external 10KHz ~ 1290Hz clock number, here by the FPGA system clock (50MHz) frequency by 256 points to be clk1 (195KHz ) as the conversion ADC0809 clock job.
- 2023-07-04 18:20:03下载
- 积分：1
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UART0407
ise平台模拟UART，并与PC机实现收发（+1）(ISE platform simulation UART and transceiver.)
- 2013-04-22 15:38:36下载
- 积分：1
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for Dictyophora board, in the way of achieving LCD clock function.
适合DE2板，能够在板子上的液晶显示器上实现时钟功能。-for Dictyophora board, in the way of achieving LCD clock function.
- 2023-08-10 07:45:03下载
- 积分：1
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用VHDL写的运动计时表程序，用Modelsim仿真已经通过，帖出来与大家分享。...
用VHDL写的运动计时表程序，用Modelsim仿真已经通过，帖出来与大家分享。-write VHDL campaign time table program, Modelsim simulation has been passed, Tie up share with you.
- 2022-01-26 05:57:13下载
- 积分：1
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basic_dff
spartan-3e vhdl fpga 输入用滑动按钮代替 输出用led代替(spartan-3e VHDL fpga input with sliding button instead of the output with led instead)
- 2012-04-23 16:40:17下载
- 积分：1
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QPSK
用VHDL语言实现QPSK调制功能和解调功能,(Using VHDL language features QPSK modulation and demodulation functions,)
- 2021-04-26 15:28:46下载
- 积分：1
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一个用于数字解调的应用程序，主要用于数字接收机的应用方面...
一个用于数字解调的应用程序，主要用于数字接收机的应用方面-A demodulator for digital applications, mainly for the application of digital receiver
- 2022-02-01 18:38:58下载
- 积分：1
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一款8位Turbo
一款8位Turbo-51的CPU软核的设计-An 8 Turbo-51" s soft-core CPU design ....
- 2022-02-25 13:52:11下载
- 积分：1
