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CME3000FPGADevelopment-
针对京微雅阁的CME300 FPGA教程，里面有几个例程，并附有源代码，初学者可尽快入门。(For Beijing micro Accord CME300 FPGA tutorial, there are a few routines, with source code, beginners can start as soon as possible.)
- 2013-08-19 18:01:21下载
- 积分：1
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quanjiaqi
4 级流水方式的8 位全加器。。。。。。(Way flow of 4 full adder 8. . . . . .)
- 2009-04-29 15:48:35下载
- 积分：1
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matlab
真是基于matlab的QPSK，格雷码，瑞利衰减信道，加性高斯白噪声仿真(Really based on matlab QPSK, Gray code, Rayleigh fading channel additive white Gaussian noise simulation)
- 2021-03-16 22:39:21下载
- 积分：1
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16位二进制转化为BCD码
此代码可以实现16位二进制和BCD码之间的转换。(This code can realize the conversion between 16 bit binary and BCD code.)
- 2018-10-31 13:31:13下载
- 积分：1
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R_I_CPU
学校实验，用Verilog实现的单周期CPU,分别实现I型、R型、指令，使用的工具为ISE(School experiments, using Verilog to achieve a single cycle CPU, respectively, to achieve I type, R type, instruction, the use of tools for ISE)
- 2018-06-11 16:38:10下载
- 积分：1
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uart
uart通信的Verilog实现,包含rx tx 以及testbench(Verilog implemention of UART telecommunicate)
- 2018-09-18 17:06:06下载
- 积分：1
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FPGA-Design
自己搜集的一些FPGA指南教程，包括一些高工们的经验之谈、设计原则，目前正在学习，有一定帮助，分享给大家(Gather their own of some FPGA guide tutorial, including some senior engineers are the voice of experience, design principles, are learning to have some help, to share to everyone)
- 2012-11-06 10:58:54下载
- 积分：1
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clock_seg
用FPGA分频，做一个有时分秒的时钟，并用数码管显示(FPGA divide a sometimes every minute clock, and digital display)
- 2013-05-20 13:53:06下载
- 积分：1
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3FP
一个三分频verilog模块，可以用来学习基本结构。(A three points frequency verilog module can be used to study the basic structure.)
- 2013-08-25 00:41:29下载
- 积分：1
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i2c_master_top
i2c core : i2c master top
- 2012-05-23 01:17:22下载
- 积分：1
