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GFverilog-hdl
伽罗华域的乘法器的设计,使用有限域设计乘法器(Galois field multiplier design, the use of finite field multiplier design)
- 2011-05-01 13:19:22下载
- 积分:1
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fullbridge_double_frequency
建立了单相的PWM整流器电路闭环控制的仿真模型。版本R2007(The simulation model of the closed-loop control of single-phase PWM rectifier circuit. Version R2007)
- 2021-02-02 09:10:00下载
- 积分:1
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USB2.0的VHDL描述,很经典了,欢迎大家下载
USB2.0的VHDL描述,很经典了,欢迎大家下载-USB2.0 the VHDL description, very classic, and welcomes everyone to download
- 2023-04-17 09:30:03下载
- 积分:1
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基于FPGA的电子时钟设计
具体设计内容计时功能:电子表的基本功能,要求用LCD显示,显示格式是时、分、秒;校时功能:用户可以更改当前时间。设置闹钟时间:用户可以设置闹钟时间,其操作过程与校时过程一样;整点报时开关:整点报时可以由用户设定为开启或关闭两种状态,当整点报时开启时,电子表会在整点时发出1秒的闹铃声(在UP3的板上用一个LED表示);闹钟功能开关:闹钟由用户设定为开启或关闭,当闹钟开关开启时,如果当前时间与设置的闹钟时间一致,发出长达10秒的闹铃声;
- 2022-11-29 04:25:04下载
- 积分:1
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RISC
32 bit RISC Processor with 3 stage pipeline
- 2010-03-03 00:09:16下载
- 积分:1
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- 2022-09-30 22:40:03下载
- 积分:1
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chuankou_huihuan
说明: FPGA与PC端实现串口数据的收发,先从PC端接收数据,然后发回给电脑,可通过串口助手验证。(The serial port data is sent and received between the FPGA and the PC. First, the data is received from the PC, and then sent back to the computer. It can be verified by the serial port assistant.)
- 2020-06-16 10:20:01下载
- 积分:1
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decode_64_66
自编的64B/66B解码程序,做毕业设计的时候写的。(The decoding process 64B/66B , written when i am in the school。)
- 2020-10-16 10:07:29下载
- 积分:1
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FFT算法的VHDL语言实现
可在Modelsim上运行和调试
FFT算法的VHDL语言实现
可在Modelsim上运行和调试 -FFT algorithm VHDL in the operation and Modelsim Debugging
- 2022-06-17 11:09:01下载
- 积分:1
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带FIFO的ov7670 FPGA应用程序,经测试可用
这是用Verilog编写的OV7670摄像头驱动代码,带FIFO,经测试可用。(This is written in Verilog OV7670 camera driver code, with FIFO, tested available.)
- 2021-04-08 21:19:00下载
- 积分:1