-
MyPCICard
是用于pci开发的核,可以将硬件的信息映射到然间上来 节省出开发人员用于了解硬件的时间 (Pci developed for nuclear, hardware information can be mapped to the inter-ran up to save the developers time to understand the hardware)
- 2008-08-10 19:49:03下载
- 积分:1
-
APB 总线
APB 总线。可以实现单个数据在总机与从机之间的读写功能(This can achieve the read and write functions of a single data between the master and the slave .)
- 2017-08-22 16:04:06下载
- 积分:1
-
math_real
in this code very useful for designing real number concept
- 2013-11-19 19:54:40下载
- 积分:1
-
用VHDL语言写的VGA核心,是个很好很齐全的核心,有很多功能.
用VHDL语言写的VGA核心,是个很好很齐全的核心,有很多功能.-write VHDL VGA core, is a very good subset of the core, has a lot of functions.
- 2022-01-26 04:58:14下载
- 积分:1
-
CCSDS预测编码
最新的CCSDS高光谱图像压缩算法标准的FPGA实现,用VHDL实现的。可参考。绝对物有所值,希望对你的设计有所帮助!
- 2022-04-18 02:18:29下载
- 积分:1
-
USB_xilinx_vhdl
Giao tiep Univesan ...
- 2020-06-20 03:00:02下载
- 积分:1
-
tcpip_stack_v1_2
说明: 实现ARP、ICMP、UDP、TCP、IP和MAC全过程的传输,对TCP的连接、接收、发送、断开均经过测试,功能正常(Realize the transmission of ARP, ICMP, UDP, TCP, IP and MAC in the whole process, test the connection, reception, transmission and disconnection of TCP, and the function is normal)
- 2020-05-05 10:03:04下载
- 积分:1
-
Xilinx,Altera,ARM,AVR,S52,Lattice等系列FPGA的下载线电路图和PCB
Xilinx,Altera,ARM,AVR,S52,Lattice等系列FPGA的下载线电路图和PCB-Xilinx, Altera, ARM, AVR, S52, Lattice series FPGA download cable circuit diagram and PCB
- 2022-03-17 00:48:42下载
- 积分:1
-
MemoryGame-master
在开发板EGO1上实现的图形记忆游戏,白块按下确认建,黑色块不按确认键(memory game in verilog)
- 2020-12-19 16:29:10下载
- 积分:1
-
mod3
verilog源代码,实现两种方法的模3运算。(verilog source code,to implement the calculation of mod-3 by two means.)
- 2011-12-24 10:23:40下载
- 积分:1