-
在SOPC Builder的UART IP核接口
UART RS232 IPCORE for sopc builder
-RS232 UART IPCORE for sopc builder
- 2022-03-04 13:15:40下载
- 积分：1
-
基本逻辑门电路的设计方法，或门的VHDL的设计让你更容易步入VHDL的设计氛围中，简单的或门编制...
基本逻辑门电路的设计方法，或门的VHDL的设计让你更容易步入VHDL的设计氛围中，简单的或门编制-Basic logic gate circuit design methods, or the door of the VHDL design allows you to more easily into the VHDL design environment, the simple OR gate preparation
- 2022-01-30 19:12:35下载
- 积分：1
-
Experiment_1_Xilinx
很不错的FPGA入门级实验指导书，按照实验的知道，能够学会使用ISE仿真简单的流水灯。教程较为详细，从硬件连接到代码编写都做了详细指导，适合新手入门。(Very good entry-level FPGA experimental guide books, according to the experiment know, be able to learn to use the ISE Simulator simple water lights. Tutorial in detail, the hardware connected to the coding have done a detailed guide for beginners.)
- 2016-09-16 23:07:26下载
- 积分：1
-
Lpfilter_20190503
说明： 环路滤波器是通信信号调制解调中最重要的一个部分，环路滤波器设计的好坏将直接影响到接收机的性能指标，二阶锁频辅助三阶锁相环路滤波器可以稳定跟踪具有加加速度的信号源，是现代通信中非常实用的技术，本文中详细编写了单载波信号产生模块、信道噪声模块、数字正交下变频模块、鉴频鉴相模块、环路滤波器模块，并包含了完整的testbench模块，对于初学者非常有用。(Loop filter is the most important part of communication signal modulation and demodulation. The design of loop filter will directly affect the performance index of receiver. The second-order frequency locking assisted third-order phase-locked loop filter can stably track the signal source with acceleration speed, which is a very practical technology in modern communication. In this paper, the single carrier signal generation module and channel noise are written in detail Sound module, digital orthogonal down conversion module, frequency and phase detection module, loop filter module, and contains a complete testbench module, which is very useful for beginners.)
- 2020-11-11 01:27:25下载
- 积分：1
-
ISE为开发环境，Verilog语言编写程序
以ISE为开发环境，Verilog语言编写程序。功能：FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)
- 2020-06-20 00:00:02下载
- 积分：1
-
SPI接口VHDL代码,内有说明,很详细.
SPI接口VHDL代码,内有说明,很详细.-SPI interface VHDL code, which has made it clear that, in great detail.
- 2022-03-31 21:18:26下载
- 积分：1
-
对行为模型的全加器的VHDL代码
工具；
- 2022-04-18 04:42:27下载
- 积分：1
-
FPGA UART的发送等
FPGA UART transmit and so on
- 2022-01-24 13:54:39下载
- 积分：1
-
18 x 18 华莱士树乘法器
经过测试的 VHDL 代码为 18 x 18 位华莱士树乘法器
- 2022-01-30 15:01:08下载
- 积分：1
-
verilog-montgomery-RSA
基于Montgoery 算法的RSA,FPGA verilog 实现，有测试文件(Based on Montgoery algorithm for RSA,FPGA verilog implementation，bench file)
- 2021-04-27 20:28:44下载
- 积分：1
