登录
首页 » VHDL » 数字电路 贪食蛇游戏

数字电路 贪食蛇游戏

于 2022-03-17 发布 文件大小:525.60 kB
0 133
下载积分: 2 下载次数: 1

代码说明:

VHDL     贪食蛇游戏用游戏把子上下左右控制蛇的方向,寻找吃的东西,每吃一口就能得到一定的积分,而且蛇的身子会越吃越长,身子越长玩的难度就越大,不能碰墙,不能咬到自己的身体,更不能咬自己的尾巴,等到了一定的分数,就能过关,然后继续玩下一关。

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 本例为电子琴VHDL程序原代码,电子琴,可实现基本功能
    本例为电子琴VHDL程序原代码,电子琴,可实现基本功能-In this case the procedures for organ VHDL source code, organ, can realize the basic functions of
    2022-03-23 15:59:38下载
    积分:1
  • 用verilog编写的乒乓球游戏,内带ps2,VGA驱动,下载到spantan3开发板上即可使用(原创)...
    用verilog编写的乒乓球游戏,内带ps2,VGA驱动,下载到spantan3开发板上即可使用(原创)-Prepared using Verilog table tennis game, with band ps2, VGA driver, download to spantan3 development board to use (original)
    2023-07-23 17:15:04下载
    积分:1
  • jiaotongdeng
    交通灯通过数码管显示,几种模式可调,还可以时间可设,适合初学者入门参考学习。(LED traffic lights can be set to several modes adjustable time beginners reference ~ ~ ~)
    2013-08-25 10:02:34下载
    积分:1
  • pro1
    对用开发板上开关产生的信息做汉明编码并通过串口发送至电脑(The Hamming code is generated from the switch on the development board and sent to the computer through the serial port.)
    2018-11-15 17:01:21下载
    积分:1
  • xapp from xilinx very hard to find and very usefull application note from the gr...
    xapp from xilinx very hard to find and very usefull application note from the great firm from USA
    2022-01-25 23:53:59下载
    积分:1
  • Advanced FPGA Design Architecture, Implementation, and Optimization
    Advanced FPGA Design Architecture, Implementation, and Optimization
    2022-02-05 23:31:15下载
    积分:1
  • 16位浮点FFT算法的VHDL实现有测试文件!
    16位浮点FFT算法的VHDL实现有测试文件!-16-bit floating-point FFT algorithm VHDL realization of a test file!
    2022-01-28 18:16:34下载
    积分:1
  • 波形发生器,带TESTBENCH, 多平台
    波形发生器,带TESTBENCH, 多平台 -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn -waveform generator, with TESTBENCH. Multi-platform-- the design makes use of the new shift opera tors available in the VHDL-93 std-- this design passes the Synplify synthesis check-- downloa d from : www.fpga.com.cn
    2023-05-18 16:15:03下载
    积分:1
  • MRAM2012
    STT-MRAM磁性存储器全部verilog代码和仿真验证代码,包括行为模块,读写模块和控制模块,已经经过验证完全正确(STT-MRAM magnetic memory all the code and simulation code, including behavior module, reader module and the control module, has been proven entirely correct)
    2020-06-29 14:20:02下载
    积分:1
  • USB
    实现FPGA与PC通信的USB2.0接口,采用verilog语言实现(Implementation of FPGA and PC communication USB2.0 interface, using Verilog language to achieve)
    2021-02-22 21:59:41下载
    积分:1
  • 696518资源总数
  • 106161会员总数
  • 5今日下载