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5_ADC_Lab
altear max10 adc demo，实验使用了2个adc，最大支持18路adc(altear max 10 demo with 2 adc， max support 18 channel adc)
- 2021-04-21 14:48:49下载
- 积分：1
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rfid new code
说明： In the data management system a significant role of the Data link layer is to convert the unreliable physical link between reader and tag into a reliable link. Therefore, the RFID system employs the Cyclic Redundancy Check (CRC) as an error detection scheme. In addition for reader to communicate with the multiple tags, an anti-collision technique is required. The technique is to coordinate the communication between the reader and the tags. The common deterministic anti-collision techniques are based on the Tree algorithm such as the Binary Tree and the Query Tree algorithms.
- 2019-04-30 16:54:27下载
- 积分：1
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b4b52
4b5b编码器实现，初学者资源，简单的逻辑电路实现(4b5b encoder implementation, resources for beginners)
- 2020-12-03 08:59:25下载
- 积分：1
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8051内核的hdl代码，实际上是verilog格式不过上载页面只有一个vhdl选择，值得一读， 里面对仿真和验证的说明很有含金量...
8051内核的hdl代码，实际上是verilog格式不过上载页面只有一个vhdl选择，值得一读， 里面对仿真和验证的说明很有含金量-the hdl code of 8051 core
- 2022-08-08 19:01:35下载
- 积分：1
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c_fir_ppt
C语言写得FIR滤波器代码，简单实用，是学习滤波器设计的好材料，附带PPT滤波器设计说明(C language written FIR filter code, simple and practical, is a good learning materials of filter design, with PPT filter design
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- 2020-07-04 03:00:02下载
- 积分：1
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PipelineCPU
Quartus II 7.2环境中，采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计(quartusII mips pipeline 32bit cpu design)
- 2010-05-26 16:51:42下载
- 积分：1
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BIT
说明： FPGA应用状态机版，适合初学者学习状态机三段式，ASMD图的理解和翻译，以及Verilog语言的应用 最后对仿真的一些理解 其中包含HDL设计及testbench描述
根据要求设计了一个能求出一个32bit字中两个相邻0之间最大间隙的电路。(FPGA application state machine version, suitable for beginners to learn state machine three-stage, ASMD chart understanding and translation, and Verilog language application. Finally, some understanding of simulation, including HDL design and testbench description
According to the requirements, a circuit is designed to find the maximum gap between two adjacent zeros in a 32 bit word.)
- 2020-04-28 15:57:34下载
- 积分：1
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digital_clock
数字钟通过verilog实现，并且支持Modelsim仿真，通过实验验证(The digital clock is implemented by Verilog and supports Modelsim simulation)
- 2020-06-18 05:00:02下载
- 积分：1
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Xilinx_FPGA_FFT_Application_Note
Xilinx FPGA中FFT IP核的使用笔记，内部有FFT硬核的端口说明和具体设置以及源代码，对于数字信号处理研究人员，能图像处理、雷达成像、实时通信开发人员较多的开发时间！(Xilinx FPGA in the FFT IP core using a laptop internal hard core of the FFT port description and specific settings as well as the source code for digital signal processing, image processing, radar imaging, real-time communications developers more development time!)
- 2013-04-23 09:34:31下载
- 积分：1
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PCI_Master
pci协议主模块开发实用代码， 适合初级学习者使用 很不错(pci agreement to develop practical code, very good for junior learners)
- 2013-01-10 14:48:24下载
- 积分：1
