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这是一个用vhdl编的多功能电子秒表，可以记录几个人的时间，并且可以在跑秒的时候查看记录。。〔原创〕...
这是一个用vhdl编的多功能电子秒表，可以记录几个人的时间，并且可以在跑秒的时候查看记录。。〔原创〕-This is a series with VHDL multifunctional electronic stopwatch, can be recorded by several people, and that they could run in the second examined the records. . [Original]
- 2022-12-02 01:35:03下载
- 积分：1
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基于DE2-70开发板的VGA接口实现程序
基于DE2-70开发板的VGA接口实现程序，可在VGA屏幕上显示800*600分辨率的图像，刷新频率60Hz
- 2022-03-12 13:00:51下载
- 积分：1
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Xcell1
W elcome to X CELL, the new
Xilinx customer newsletter.
By sending us your development
system registration card you automatically
became n charter subscriber
to this quarterly publication. It is our
intent to make this an informative,
easy to read, responsive and-hopefully-
interactive newsletter. We
want to supply you with early and
correct information, tell you about
the status of our products and about
our plans, about bugs and their workarounds,
give you applications ideas
and convey to you some of the en thusiasm
that we feel for our Programmable
Gate Arrays.
If you have questions or suggestions,
please send them to me. II Letters
to the Editor make a newsletter
more lively.
Peter Alfke, Editor
- 2014-12-25 01:07:59下载
- 积分：1
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ug848-VC707-getting-started-guide
vc707 board getting started guide
- 2018-06-14 05:52:39下载
- 积分：1
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dct1d核心的FPGA实现
应用背景为了实现良好的压缩性能，相关性颜色分量RGB颜色空间转换到去相关的色彩空间首先减少。在基线JPEG，一个RGB图像转化成亮度chrominancc如YCbCr颜色空间。将图像的亮度色度空间的优势的亮度和色度分量非常不相关彼此之间。此外，色度通道包含大量冗余信息可以很容易地被采样不牺牲任何视觉质量对于重建图像。从RGB到YCbCr的转换，是基于以下的数学表达：关键技术应用DCT变换，将图像划分成8´8像素块。如果原始图像的宽度或高度是不能被8整除，编码器必须整除。8´8块进行处理，从左到右，从上到下。和公司；及；及；及；及；及；及；及；及；DCT变换的像素值的空间频率。这些空间频率是非常相关的细节目前在一个图像的水平。高空间频率对应于高层次的细节，而较低频率对应于较低的细节层次。数学定义DCT是：
- 2022-07-03 22:27:28下载
- 积分：1
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vhdl编的dds函数发生器，完成sin(x)曲线的生成
vhdl编的dds函数发生器，完成sin(x)曲线的生成-vhdl function generator dds compiled to complete the sin (x) curve is generated
- 2022-07-02 02:04:16下载
- 积分：1
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1
说明： 单周期cpu，使用verilog编写的的单周期cpu支持......等功能(Single cycle CPU, using Verilog written single cycle CPU support... And other functions)
- 2021-03-15 08:45:07下载
- 积分：1
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uart_test
verilog实现UART收发功能，硬件平台为spartan 6，软件平台为ise14.7(verilog implement UART rx and tx function)
- 2017-10-07 16:34:13下载
- 积分：1
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Altera公司的DE2平台的VGA接口的应用程序，从上到下KEY0
ALTERA的DE2平台VGA接口应用，由KEY0－KEY3控制上下左右，使屏幕上光标移动，由Verilog描述。-ALTERA the DE2 platform VGA interface applications, from top to bottom KEY0-KEY3 about control, so that the screen cursor by the Verilog description.
- 2022-09-28 16:00:04下载
- 积分：1
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buffer for in/out data.
buffer for in/out data.
- 2023-02-22 20:05:04下载
- 积分：1
