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CORDIC 代码
说明： Xilinx CORDIC 算法 MATLAB Verilog仿真(arctan.m Kn.m sin_cos.m MATLAB Verilog)
- 2019-03-27 09:53:35下载
- 积分：1
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dds32_1
说明： 频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序(Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program)
- 2011-04-14 13:45:22下载
- 积分：1
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CameraTrackingmaster
moving tracking based in D5M camera
tracking camera
- 2016-04-08 14:57:11下载
- 积分：1
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dft
verilog语言实在点变换DFT源代码，可以配合软核或者其他CPU进行综合FFT变换，也可以单独使用生成module！(verilog language is point FFT transform source code, can tie in with the soft-core CPU, or other integrated FFT transform, it can be used to generate module!)
- 2009-05-09 14:29:47下载
- 积分：1
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turbo
详细讲述TURBO码的FPGA实现原理，可作参考，不是码源(A detailed account of the FPGA implementation of principle of the TURBO code can be used as reference, not source code)
- 2012-05-01 13:12:59下载
- 积分：1
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ROM模块，功能在于，是创建一个简易的rom模块
ROM模块，功能在于，是创建一个简易的rom模块-rom
- 2022-03-31 16:48:46下载
- 积分：1
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Send-Program
program send sms by sim900 module
- 2012-08-08 18:25:11下载
- 积分：1
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hdl
网上流传的用来实现FPGA驱动VGA，从而实现一个pingpong小游戏的源码，实测可用。(a program embedded in a FPGA in order to drive the VGA and realize a little game named pingpong.
tested.)
- 2009-03-31 22:36:37下载
- 积分：1
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内附多路选择器，74系列芯片VHDL源码，加法器，FIR，比较器等大量例子，对初学VHDL语言很有好处。可用maxplus，quartus，synplicity...
内附多路选择器，74系列芯片VHDL源码，加法器，FIR，比较器等大量例子，对初学VHDL语言很有好处。可用maxplus，quartus，synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging
- 2022-08-11 02:50:00下载
- 积分：1
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lcd1602_drive
用Verilog实现1602的配置及功能。正确编译与实现(Realized by Verilog 1602 configurations and functions. Compilation and implementation of the right)
- 2011-01-21 16:47:27下载
- 积分：1
