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用verilog写的cpld的各种分频程序,希望大家指正,谢谢!
用verilog写的cpld的各种分频程序,希望大家指正,谢谢!-using Verilog cpld written by the various sub-frequency procedures in the hope that we stand corrected, thank you!
- 2023-01-20 06:35:04下载
- 积分:1
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使用vhdl语言实现对led的控制,还有电路仿真
使用vhdl语言实现对led的控制,还有电路仿真-Using vhdl language implementation of the led control, as well as circuit simulation
- 2022-03-12 11:40:55下载
- 积分:1
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crc校验,经验证正确,下载就可直接用,有不足的地方可以指正,
crc校验,经验证正确,下载就可直接用,有不足的地方可以指正,-CRC check, certified correct, you can download directly, there are deficiencies can correct me,
- 2022-10-07 11:55:03下载
- 积分:1
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VHDL开发环境,出租车计费系统,实现起步10元,每增加一公里,自动上涨2元。...
VHDL开发环境,出租车计费系统,实现起步10元,每增加一公里,自动上涨2元。-VHDL development environment, taxi billing system to achieve the initial 10 yuan for each additional mile, automatic up 2.
- 2022-03-26 01:55:17下载
- 积分:1
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hilbert_m
基于FPGA的希尔伯特变化的verilog代码(Hilbert change verilog code)
- 2020-10-19 09:37:25下载
- 积分:1
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PCIe_Lab(ALTERA-V5PCIe)
这一设计实例深入浅出,介绍怎样产生一个Qsys子系统。 您将产生一个含有以下组成的Qsys系统:在Cyclone IV GX收发器入门套件上,设计带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器。
(Qsys system: the Cyclone IV GX Transceiver Starter Kit, designed with embedded transceivers Gen1 × 1 hard IP PCI Express IP compiler.)
- 2020-12-02 18:39:25下载
- 积分:1
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vga_ctl_640x480
VGA 640x480 driver in verilog
- 2010-08-16 02:48:43下载
- 积分:1
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用vhdl描写的通用异步改进dram控制器,经过编译器综合和仿真测试,符合设计要求。...
用vhdl描写的通用异步改进dram控制器,经过编译器综合和仿真测试,符合设计要求。-Using VHDL description Universal Asynchronous improved dram controller, through an integrated compiler and simulation testing, in line with the design requirements.
- 2022-04-19 09:59:57下载
- 积分:1
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DDS
Verilog实现DDS线性调频,Verilog实现DDS线性调频(Verilog implementation of DDS linear FM,Verilog implementation of DDS linear FM)
- 2015-07-29 19:59:36下载
- 积分:1
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MUX
说明: 用CASE实现4选1数据选择器 很实用 运用VERILOG(Using CASE to achieve 4 election 1 Data Selector practical use Verilog)
- 2008-09-11 11:37:35下载
- 积分:1