-
VHDL_ 两个电路计数上 / 下液晶显示语言 VHDL (海 mạch đếm lên/xuống hiển 施耐液晶 bằng ngôn ngữ VHDL)
VHDL_ 两个电路计数上 / 下液晶显示语言 VHDL (海 mạch đếm lên/xuống hiển 施耐液晶 bằng ngôn ngữ VHDL)
- 2022-02-03 20:36:30下载
- 积分:1
-
RS232 data transmitter, suitable for beginners VHDL reference
RS232数据发送器,适合于VHDL的初学者参考-RS232 data transmitter, suitable for beginners VHDL reference
- 2022-03-15 09:13:00下载
- 积分:1
-
The VHDL source code digital clock, you can achieve at school, school grade feat...
数字钟的VHDL源程序,可以实现校时,校分等功能,并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on
- 2023-02-06 10:05:04下载
- 积分:1
-
EPM570并串转换器
基于CPLD器件EPM570,用VHDL语言编写的并串转换器代码,用于实现并行代码到串行代码的转换
- 2022-07-13 17:44:24下载
- 积分:1
-
FPGA_design
成功解决FPGA设计时序问题的三大点.word说明文档,很详细(FPGA design timing problems successfully solved the three points)
- 2010-07-19 16:16:28下载
- 积分:1
-
carry_lookahead_add4
4位的超前进位加法器,门级电路连接得到,verilog代码实现(4-bit look-ahead adder, gate-level circuit)
- 2011-10-18 21:40:20下载
- 积分:1
-
Interleaver
基于FPGA实现交织 在通信中交织的算法 已在板上通过测试(based on FPGA to Interleaver)
- 2018-02-01 20:54:13下载
- 积分:1
-
0_09_uart_tx
说明: 在FPGA板卡上面,通过单个按键实现串口的发送功能,带仿真需要自行修改一下工程配置(On the FPGA board, the sending function of the serial port is realized by a single key, and the engineering configuration needs to be modified by the simulation)
- 2020-03-26 08:40:39下载
- 积分:1
-
FPGA加密的方法,对于那些需要加密自己的vhdl源代码的人来说,很有用...
FPGA加密的方法,对于那些需要加密自己的vhdl源代码的人来说,很有用-FPGA encryption methods for those who need to encrypt their VHDL source code in a way, very useful
- 2022-11-20 11:40:03下载
- 积分:1
-
用Verlog HDL编写的数字钟程序,包含时,分,秒,进位,解码,扫描显示等功能。...
用Verlog HDL编写的数字钟程序,包含时,分,秒,进位,解码,扫描显示等功能。-Written by Verlog HDL ,a digital clock program, including hours, minutes, seconds, into the place, decoding, scanning display.
- 2023-02-05 04:55:03下载
- 积分:1