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9826
针对AD9826驱动设计的Verilog代码，主要是配置ccd采样的设计(The Verilog code is designed for AD9826, to configuration ccd sampling )
- 2020-07-16 21:48:50下载
- 积分：1
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FPGA控制的SRAM接口不分的设计
FPGA控制的SRAM接口不分的设计-FPGA-controlled SRAM interface design, regardless of
- 2023-02-19 02:15:03下载
- 积分：1
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这是我的毕业设计的SVPWM使永磁交流同步电动机…
这是我毕业设计做的一个SVPWM同步永磁交流电机的控制系统，里面除了一个SVPWM的驱动算法之外，还有一个步进电机的控制器，以及基于QUARTUS7.2的NIOS II控制核心，通过PC的串口可以控制同步永磁交流电机和步进电机进行精确的定位。该系统较复杂，运用的知识也比较多，在SVPWM算法，PID算法，步进电机控制方面，NIOS II的串口编程等都有值得参考的地方。最好使用QUARTUS7.2编译，目标芯片是选用EP1C6Q240-This is my graduation project SVPWM make a permanent magnet AC synchronous motor control system, which apart from a driver SVPWM algorithm, there is a stepper motor controller, as well as QUARTUS7.2 based on the NIOS II control core, through PC serial port can be controlled permanent magnet AC synchronous motor and stepper motor for accurate positioning. The system is more complicated, the use of more knowledge, in the SVPWM algorithm, PID algorithm, stepper motor control, NIOS II serial programming, such as places are worth considering. QUARTUS7.2 compile the best use of the target chip is optional EP1C6Q240
- 2023-05-08 19:40:04下载
- 积分：1
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4jieshuzilboqi
四阶数字滤波器 用不同的算法设计数字滤波器，并且有详细的是用方法(Fourth-order digital filter design with a different digital filter algorithms and a detailed method is)
- 2011-04-25 18:18:16下载
- 积分：1
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key_debounce-source-code
这是fpga按键消抖的源代码，在很多fpga按键实验中都可以用到，能够进行代码移植。(This is the source code of the FPGA buttons, in many FPGA key experiments can be used, and can carry out code.)
- 2015-10-31 10:19:03下载
- 积分：1
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stop_watch
采用Quartus2编写的电子秒表电路
实现计时、暂停等功能(Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions)
- 2008-04-27 13:04:03下载
- 积分：1
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Harris-algorithm-based-on-FPGA
在利用FPGA的并行处理能力应对高速数据和去做复杂的数据处理时，对一些较为复杂或者重复性工作模块多的情况下，算法资源就需要进行预评估。有效的资源预评估不仅可以在芯片选型上有益，还可以对程序有较详细的估计，在硬件不变的前提下能够选择更好的算法优化。本文着重在Harris算法在FPGA的实现以及在移植之前对其占用的FPGA资源进行预评估。(Response to high-speed data and do complex data processing in the FPGA parallel processing capabilities, to cope with some of the more complex or repetitive tasks module，it is necessary to pre-assessment algorithm resources. Resources pre-assessment can not only be useful in the chip selection, but also be a more detailed estimate of the program to be able to choose a better algorithm optimization in the same premise hardware. This article focuses on the pre-assessment in the Harris algorithm in the FPGA implementation and its FPGA resources occupied prior to transplantation.)
- 2013-02-28 15:41:39下载
- 积分：1
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方形伺服电机 vhdl
PROGRAMM有助于使40厘米见方与FPGA机器人改变board.The运动遵循顺时针旋转。此外，惯性中心的旋转过程中保持不动。
- 2022-02-14 00:56:00下载
- 积分：1
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uart串行口,用Verilog编写的.供大家参考
uart串行口,用Verilog编写的.供大家参考-uart serial port, using Verilog prepared. For your reference
- 2022-07-17 22:14:09下载
- 积分：1
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CORDIC 代码
Xilinx CORDIC 算法 MATLAB Verilog仿真(arctan.m Kn.m sin_cos.m MATLAB Verilog)
- 2019-03-27 09:53:35下载
- 积分：1
