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verification environment to verify synchronous FIFO
-&同步FIFO的验证环境。
- 2022-12-14 19:40:03下载
- 积分：1
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05_fifo_test
说明： FIFO: First in, First out 代表先进的数据先出，后进的数据后出。Xilinx 在 VIVADO 里为我们已经提供了 FIFO 的 IP 核, 我们只需通过 IP 核例化一个 FIFO，根据 FIFO 的读写时序来写入和读取FIFO 中存储的数据。(FIFO: first in, first out represents the first out of advanced data, and the last in data is the last out. Xilinx has provided us with the IP core of FIFO in vivado. We only need to instantiate a FIFO through the IP core, and write and read the data stored in FIFO according to the FIFO read-write timing.)
- 2021-04-08 22:19:20下载
- 积分：1
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DDS_AD9910
说明： 用 AD9910实现的DDS 线性调频信号,调试已通过 可以使用(DDS LFM signal realized by ad9910 has passed debugging and can be used)
- 2019-10-23 15:36:06下载
- 积分：1
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chaotic_1d
说明： 一维超混沌随机数的生成verilg，还有testbench仿真激励，modelsim的仿真工程。(The generation of one-dimensional hyperchaotic random number verilg, testbench simulation stimulation and Modelsim simulation engineering.)
- 2020-05-11 12:45:42下载
- 积分：1
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时钟分频的 verilog
时钟司程序测试所选定的值 （32 位）。填空 Altera QuartusII Verilog。
- 2022-04-08 14:58:17下载
- 积分：1
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fft source code
FFT源代码64。
- 2023-04-12 02:35:03下载
- 积分：1
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ADC_Ctrl
简单的12位的AD转换实现，模数转换，实现模拟量转化为数字量，并在液晶显示屏上显示出转化结果，我自己下载到板子，运行正常.
- 2022-03-26 09:04:08下载
- 积分：1
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FSK
2FSK的matlab仿真，叠加了高斯白噪声(2FSK matlab simulation, superimposed on a Gaussian white noise)
- 2021-04-13 02:58:56下载
- 积分：1
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spi
该程序是一个可完成订制化的SPI双向总线接口，时钟相位、极性，以及分频比全部可通过寄存器进行配置，已经在ISE下通过综合，占用资源少，强烈推荐
(The program is a complete custom of SPI bidirectional bus interface, clock phase, polarity, and the divider ratio can all be configured through the register, has been in the ISE through an integrated, small footprint, it is strongly recommended)
- 2013-07-02 14:07:16下载
- 积分：1
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verilog8
Learning Verilog Chinese Version Part 8
- 2012-06-15 06:04:00下载
- 积分：1
