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multiDDC
Multi-Digital Down Converter design.
- 2008-11-23 15:26:35下载
- 积分:1
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A_PUF_Design
基于fpga的物理不可克隆函数(PUF)模块的实现(A PUF Design for Secure FPGA-Based Embedded Systems)
- 2014-06-28 15:37:44下载
- 积分:1
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EDA VHDL modules commonly used procedure, the time
EDA中常用模块VHDL程序,不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ,25分频=2HZ,10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)
- 2022-07-02 21:52:46下载
- 积分:1
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ADS1115
本程序调试了TI的高精度模数转换芯片ADS1115,此模数转换器采用双积分型,16位,为IIC通信方式,调试较复杂,在对直流采集方面有着广泛的应用(This program debugging TI s high-precision analog-digital conversion chip ADS1115)
- 2013-08-23 22:49:26下载
- 积分:1
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ALU_4bit
4位ALU,有两个4位输入,4位输出实现逻辑运算和算术运算,逻辑与或非,加1,减1等等功能(4 ALU, logical and arithmetic operations)
- 2012-11-18 18:04:59下载
- 积分:1
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1.初始状态为4个方向的红灯全亮,时间1秒。
2.东、西方向绿灯亮,南、北方向红灯亮。东、西方向通车,时间30秒。
3.东、西方向黄灯闪烁,南、北方...
1.初始状态为4个方向的红灯全亮,时间1秒。
2.东、西方向绿灯亮,南、北方向红灯亮。东、西方向通车,时间30秒。
3.东、西方向黄灯闪烁,南、北方向红灯亮。时间2秒。
4.东、西方向红灯亮,南、北方向绿灯亮。南、北方向通车,时间15秒。
5.东、西方向红灯亮,南、北方向黄灯闪烁。时间2秒。
6.返回2,继续运行。
-1. Initial state for four whole direction of the red lights lit up, a second time. 2. East and West to the green, in the south, north to the red light. West and the East to open in time for 30 seconds. 3. East and West to the blinking yellow light, in the south, north to the red light. Time 2 seconds. 4. East and West to the red light, in the south, north to the green. South and North to the opening time of 15 seconds. 5. East and West to the red light, in the south, north to the flashing yellow light. Time 2 seconds. 6. Return 2, continued to operate.
- 2023-01-12 03:20:04下载
- 积分:1
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基于vhdl的PWM发生器
基于vhdl的PWM发生器-VHDL-based PWM generator
- 2022-03-04 15:27:12下载
- 积分:1
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本例为DAC0832接口电路VHDL原代码
本例为DAC0832接口电路VHDL原代码-The DAC0832 Interface Circuit Example for VHDL source code
- 2022-08-14 02:36:10下载
- 积分:1
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iq_balance
调整iq幅度不平衡的模块,可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)
- 2021-04-23 17:48:47下载
- 积分:1
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Verilog HDL编写的CPU模型,很经典,比较通用
Verilog HDL编写的CPU模型,很经典,比较通用-Verilog HDL prepared by the CPU model, classic, more generic
- 2022-03-21 08:58:27下载
- 积分:1