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基于FPGA的交通灯的设计 有Verilog HDL 源码、仿真图与引脚配置图，已下载实现...
基于FPGA的交通灯的设计 有Verilog HDL 源码、仿真图与引脚配置图，已下载实现
-FPGA-based design of traffic lights have Verilog HDL source code, simulation map with pin configuration map has been downloaded realize
- 2022-06-27 19:08:32下载
- 积分：1
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VHDL programming language introduced the basic grammar, and some programming exa...
介绍了ＶＨＤＬ编程语言的基本语法，和一些编程实例-VHDL programming language introduced the basic grammar, and some programming examples
- 2023-02-13 15:55:04下载
- 积分：1
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大唐电信的FPGA设计经验，内部资料，详细完整，很有参考价值...
大唐电信的FPGA设计经验，内部资料，详细完整，很有参考价值-Datang Telecom
- 2022-03-04 13:47:05下载
- 积分：1
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24小时计时时钟
说明： 实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)
- 2020-06-23 19:40:01下载
- 积分：1
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93 std
-- Booth Multiplier
-- This file contains all the entity-architectures for a complete
-- k-bit x k-bit Booth multiplier.
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn--- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check-- download from : www.fpga.com.cn
- 2022-02-25 16:35:00下载
- 积分：1
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AHB-answers
这个文档回答了很多关于AHB总线在使用上经常遇到的问题(this doc gives a lot of answers for using AHB bus when doing design)
- 2020-10-21 12:17:24下载
- 积分：1
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uart串行口,用Verilog编写的.供大家参考
uart串行口,用Verilog编写的.供大家参考-uart serial port, using Verilog prepared. For your reference
- 2022-07-17 22:14:09下载
- 积分：1
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IDT7005
双端口静态RAM的VHDL程序，具体芯片型号为IDT7005(DUAL-PORT
STATIC RAM)
- 2014-04-03 11:40:53下载
- 积分：1
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SoftCore_LED80-master
说明： 使用VHDL实现的LED-80分组密钥，相对于其它密钥具有硬件实现面积更小的特点(vhd code of a lightweight block cipher LED-80)
- 2020-03-24 20:57:31下载
- 积分：1
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AXI-HP-PDMAPGIC
本文参考了Xilinx 官方文档UG873，“System Design Using Processing System High
Performance Slave Port”。主要实现了PL 中AXI CDMA IP 与PS 部分HP64bit 从接口集成。
本例中AXI CDMA 部分扮演主机，从PS 部分DDR 系统内存中源缓冲区拷贝一列数据到目
的缓冲区。可以分别采用裸机工程和基于Linux 的应用软件来实现功能。(This reference to the official document Xilinx UG873, " System Design Using Processing System High Performance Slave Port" . The main achievement of the PL in AXI CDMA IP interface integration with PS part HP64bit. In this example AXI CDMA part to play host, a copy of a column of data into the destination buffer section PS source DDR system memory buffer. Can respectively bare engineering and Linux-based applications to achieve functional.)
- 2014-12-23 10:27:24下载
- 积分：1
