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Project12112011
Program for Code Gerneration
- 2011-11-13 19:14:08下载
- 积分：1
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complete with verilog language development USB2.0 IP source code, including docu...
完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
- 2022-08-22 09:20:17下载
- 积分：1
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ADS1115
本程序调试了TI的高精度模数转换芯片ADS1115,此模数转换器采用双积分型，16位，为IIC通信方式，调试较复杂，在对直流采集方面有着广泛的应用(This program debugging TI s high-precision analog-digital conversion chip ADS1115)
- 2013-08-23 22:49:26下载
- 积分：1
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20190718
说明： uart implementation and documentation, this describes the basic steps in building your own uart module on verilog and programming them on an fpga device
- 2020-06-21 21:40:01下载
- 积分：1
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vhdl
vhdl code for internet interface
- 2014-12-04 04:58:04下载
- 积分：1
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timescale-1ns
说明： 这是一款由晶振产生的脉冲控制的数字钟，可以从00:00:00到23:59:59之间进行计时。(this is a clolk controlled by continuious pulse.it can timing from 00:00:00 to 23:59:59.)
- 2011-04-13 19:21:39下载
- 积分：1
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MP3
MP3解码的ASIC全部过程，包换含c和vhdl代码，样例。(MP3 decoding ASIC whole process, shifting with c and vhdl code, sample.)
- 2021-01-02 22:48:57下载
- 积分：1
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blif2vhdl格式转换工具
A BLIF to VHDL converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included).
- 2023-06-13 19:10:02下载
- 积分：1
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FPGAPVC_3
基于SDRAM的PCI采集,上位机为VC编写，桥芯片为PLX9054，项目已经做完，上传5个例程，已经验证通过(SDRAM, PCI-based acquisition, PC for VC preparation, bridge chip for PLX9054, the project has been done, upload 5 routines, has been verified by)
- 2015-01-07 22:53:10下载
- 积分：1
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Verilog module containing a synthesizable CRC function
//* polynomial: (0 1 8)...
Verilog module containing a synthesizable CRC function
// * polynomial: (0 1 8)
// * data width: 8-Verilog module containing a synthesizable CRC function
//* polynomial: (0 1 8)
//* data width: 8
- 2022-08-18 21:19:43下载
- 积分：1
