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cic_dec_8_three
CIC 文件的ＶＨＤＬ
cic_dec_8_three
CIC 文件的ＶＨＤＬ-cic_dec_8_threeCIC documents VHDL
- 2023-03-30 12:50:03下载
- 积分：1
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74ls165
74ls165电路源代码verilog,已经验证。(74ls165 verilog)
- 2020-11-22 22:59:34下载
- 积分：1
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FPGA实现四位数与四位数乘法
FPGA实现四位数与四位数乘法，有仿真波形，合理利用FPGA资源(Four-digit and four-digit multiplication is realized by using FPGA. It has simulation waveform and makes rational use of the resources of the FPGA.)
- 2020-06-21 00:00:02下载
- 积分：1
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vhdl
code for fft non synthesisable in xilinx ise
- 2013-09-30 13:16:13下载
- 积分：1
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Digital Design and Modeling with VHDL and Synthesis
Digital Design and Modeling with VHDL and Synthesis
- 2023-06-22 18:35:14下载
- 积分：1
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UG586-7SeriesDMIUserGuide
UG586 - Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB )(UG586- Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB ))
- 2015-02-05 20:02:21下载
- 积分：1
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在利用Verilog在FPGA平台上输出正弦波，实现芯片为Cyclone II 484C8，有管脚分配...
在利用Verilog在FPGA平台上输出正弦波，实现芯片为Cyclone II 484C8，有管脚分配-In the use of Verilog in the FPGA platform, the output sine wave, the realization of the chip for Cyclone II 484C8, has pin allocation
- 2022-01-31 10:21:02下载
- 积分：1
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FPGAshixu
FPGA经验总结：时序是设计出来的
我们在做详细设计的时候，对于一些信号的时序肯定会做一些调整的，但是这种时序的调整最多只能波及到本一级模块，而不能影响到整个设计。(FPGA Experience: Timing is designed to do the detailed design of our time, for some signal timing will certainly make some adjustments, but adjust this timing can only spread to up to this level of the module, but not affect the whole design.)
- 2015-03-13 10:27:51下载
- 积分：1
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sqrt_pipeline
说明： Matlab - to hdl code for square root
- 2020-06-17 12:20:02下载
- 积分：1
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EP2C70F896C6N-pins
将VHDL程序下载到DE2开发板，引脚分配时需要知道的芯片每个引脚功能(VHDL program will be downloaded to the DE2 development board, you need to know when the pin assignments for each pin of the chip functions)
- 2020-12-09 11:09:21下载
- 积分：1
