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基于VHDL+FPGA的DDS信号发生设计，已经通过调式
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2581
Complex of three-point Gauss-lengend the Formula pi, Including orbital maneuvering simulation, initial orbit calculation, University of numerical analysis algorithms.
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出租车模块设计加nios2设计cup程序代码
出租车模块设计加nios2设计cup程序代码...
出租车模块设计加nios2设计cup程序代码
出租车模块设计加nios2设计cup程序代码-Taxi modular design design cup plus nios2 code taxi modular design design cup plus nios2 code
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webserver_c3
The term web server can refer to either the hardware (the computer) or the software (the computer application) that helps to deliver web content that can be accessed through the Internet.(web server)
- 2014-03-23 20:00:14下载
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Verilog 编写的网卡DM9000A的IP核，altera公司寄的DE2系统中的源程序核...
Verilog 编写的网卡DM9000A的IP核，altera公司寄的DE2系统中的源程序核-Verilog prepared DM9000A the IP core network card, altera company sent DE2 System source of nuclear
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verilog motor control
verilog motor control
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ALU_verilog
用verilog语言编写的4位算术逻辑单元ALU,功能参考74181，包含.v文件以及测试用.vwf文件(Verilog languages with four arithmetic logic unit ALU, functional reference to 74,181, including. V documents and testing. Vwf document)
- 2008-08-15 11:36:51下载
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48_4.12
网络通信中的MII接口
通常将4位nibble数据送出，此程序将4位数据组合成8位数据并行输出（8比特==1个字节）。。完全可用
同时包含84转换(The MII network interface usually sent four nibble data, this procedure will be 4-bit data into 8-bit parallel output data (8 bits == 1 byte). . Completely available at the same time contains 84 conversion)
- 2009-04-21 13:43:45下载
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VHDLdepinlvji
基于VHDL的数字频率计的设计.pdf
基于VHDL的频率计设计 很好用的 希望要用的同志来下载 (基于VHDL的频率计设计 很好用的 希望要用的同志来下载 )
- 2020-07-14 09:38:51下载
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Circular_Buffer，流水线型多位缓存器，verilog语言描述。通过modelsim 6。0仿真，quartus 综合通过。...
Circular_Buffer，流水线型多位缓存器，verilog语言描述。通过modelsim 6。0仿真，quartus 综合通过。-Circular_Buffer, type a number of buffer lines, verilog language description. Through modelsim 6. 0 simulation, quartus integrated through.
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