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verilogdct
dct实现verilog hdl的数字图像处理，源代码(dct achieve verilog hdl digital image processing, source code)
- 2020-12-02 17:49:26下载
- 积分：1
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Generate_4fsk
雷达信号产生4PSK简单脉冲信号很好用信号产生(Radar signal pulse signal generating 4PSK simple signal generating good)
- 2013-06-22 23:10:05下载
- 积分：1
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responder3
说明： 基于VHDL的多路抢答器，用LCD12864进行显示(Multiplex answering device based on VHDL is displayed with LCD12864)
- 2019-06-17 15:29:31下载
- 积分：1
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基于FPGA的vga显示
实现基于FPGA的vga显示，亲测能编译得过，不同开发版应该要相应改动（PS: 不太了解）
- 2022-08-09 04:41:39下载
- 积分：1
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Chapter2
通信IC设计的第二章Verilog参考学习代码，方便初学者学习入门，供学习参考用The codes of Chapter1 of《Communication IC Design》(The codes of Chapter2 of《Communication IC Design》)
- 2017-03-07 15:47:04下载
- 积分：1
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ZBT-sram控制器VHDL.doc
----------------------------------------------------------------------------------
-- Company: VISENGI S.L. (www.visengi.com) - URJC
FRAV Group (www.frav.es)
-- Engineer: Victor Lopez Lorenzo (victor.lopez (at)
visengi (dot) com)
--
-- Create Date: 12:39:50 06-Oct-2008
-- Pr
- 2022-03-02 23:54:43下载
- 积分：1
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Moltiplicatore-FP
moltiplicatore floating point
- 2009-05-12 20:26:28下载
- 积分：1
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01_test
FPGA测试程序，仅供测试硬件是否能够运行，主要功能是点亮运行指示灯(The main function of the test program of FPGA is to light the running indicator.)
- 2019-06-20 03:21:28下载
- 积分：1
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QPSK_System
实现QPSK系统的调制解调仿真，基带成形滤波器采用升余弦滚降滤波器，将仿真的误码率与理论误码率作了比较(Implement QPSK modulation and demodulation simulation system, the baseband shaping filter using Raised Cosine filter will BER simulation were compared with the theoretical BER)
- 2020-12-22 15:39:07下载
- 积分：1
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i2s_input
基于FPGA的i2s接口输入模块设计，其中有原理图和verilog源码，可在Quartus环境下进行仿真(FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment)
- 2020-12-14 16:49:14下载
- 积分：1
