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primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used stora...
本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
- 2022-07-07 05:54:22下载
- 积分：1
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interr_timer0
interruption routine for PIC16F877
- 2009-12-30 00:43:05下载
- 积分：1
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四位静态数码管控制器，含详细的中文注释，ＶＥＲＩＬＯＴ源码．...
四位静态数码管控制器，含详细的中文注释，ＶＥＲＩＬＯＴ源码．-4 static digital tube controller, with detailed notes in Chinese, VERILOT source.
- 2022-03-29 22:12:43下载
- 积分：1
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powerlink开源的最新全部源码
powerlink最新的开源全部VHDL及C/C++代码，用于powerlink的开发。是当前最新版本。包含Linux的实现及nios /arm软核的实现。可以用于xinx和Altera的FPGA。
- 2022-07-10 04:47:40下载
- 积分：1
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Features: Based on the VHDL language, realize high
功能：基于VHDL语言，实现对高速A/D器件TLC5510控制-Features: Based on the VHDL language, realize high-speed A/D control devices TLC5510
- 2022-11-12 08:45:02下载
- 积分：1
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fpga_sdram_inst
nios学习资料，fpga调用外部sdram实例，值得初学者下载。(nios learning materials, fpga call external sdram instance, it is worth beginners to download.)
- 2013-08-24 22:26:31下载
- 积分：1
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讲解用FPGA及其他芯片组成视频处理的电路设计和PFGA的程序的实现...
讲解用FPGA及其他芯片组成视频处理的电路设计和PFGA的程序的实现-Explain the use of FPGA and other video processing chips of the circuit design and FPGA realization of the procedure
- 2022-06-12 17:12:42下载
- 积分：1
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dec
A Dec example written in VHDL.
- 2009-09-23 08:57:25下载
- 积分：1
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FPGA_DSP
《FPGA数字信号处理与工程应用实践附光盘》配套源代码(FPGA DSP and their applications with verilog HDL)
- 2020-07-01 16:00:01下载
- 积分：1
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人脸识别（3D）
说明： 基于高清视频的3D人脸识别源代码，四万多行，经过FPGA实际验证，最近调试完毕。(The source code of 3D face recognition based on HD video, more than 40,000 lines, has been verified by the actual FPGA, and has been debugged recently.)
- 2019-07-01 16:22:46下载
- 积分：1
