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Altera-LVDS_IP
自己总结的Altera_LVDS的IP核的设计及仿真分析,已在实际工程中应用到,并且带有源代码和仿真代码,总结的文档,非常有用。(My summary of the Altera_LVDS IP kernel design and simulation analysis, has been applied in practical engineering, and with source code and simulation code, summary of the document, very useful.)
- 2020-12-16 14:39:13下载
- 积分:1
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计算机组成原理课设
计算机组成原理课程设计代码,课程设计,计组(Computer organization principle curriculum design code, curriculum design, group calculation)
- 2018-10-31 22:26:09下载
- 积分:1
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dw_apb_rtc_db
verilog实现rtc文档,可用于实现RTC。(verilog realize rtc document can be used to implement the RTC.)
- 2016-04-05 22:39:37下载
- 积分:1
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yidong_top_xu
本实验实现了一个小的乒乓游戏,VGA显示,代码下载的FPGA板子上验证通过,效果很好。(The experimental realization of a small ping-pong game, VGA display, download the code verified by the FPGA board, with good results.)
- 2011-11-01 19:37:44下载
- 积分:1
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altera_reed_solomon_design
altera 的reed solomn 设计(reed solomn design from altera)
- 2009-06-14 15:39:32下载
- 积分:1
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A3P600-PQG208
Actel FPGA A3P600最小系统原理图,包含JTAG 、电源和封装 (Actel FPGA A3P600 minimum system schematics, including JTAG, power and packaging)
- 2012-12-03 11:29:19下载
- 积分:1
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适用于FPGA的SOPC方面的程序开发方面,可以用于添加COMPENENT
适用于FPGA的SOPC方面的程序开发方面,可以用于添加COMPENENT-Applicable to FPGA-SOPC procedures development, can be used to add COMPENENT
- 2022-03-01 05:39:53下载
- 积分:1
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dds32_1
说明: 频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序(Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program)
- 2011-04-14 13:45:22下载
- 积分:1
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同步FIFO功能,通过Modelsim仿真Verilog语言描述6…
同步FIFO功能,verilog语言描述,通过了modelsim 6.0 仿真,Quartue综合-Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated
- 2022-03-24 20:37:31下载
- 积分:1
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ADS8325caiyang konfgzhi
ADS8325caiyang konfgzhi
- 2023-04-14 05:15:03下载
- 积分:1