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Listingprogram1
listing program clock
- 2012-11-26 03:31:42下载
- 积分：1
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DE2_SD_Card_Audio
FPGA开发,DE2开发板上实现,从SD卡读出MP3文件并播放,(即是开发一个简单的MP3播放器)(FPGA development, DE2 development board realize, from the SD card to read out and play MP3 files, (that is, the development of a simple MP3 player))
- 2020-11-28 21:49:28下载
- 积分：1
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pipline_lms_and_rls_verilog
流水线LMS，和RLS算法的Verilog代码，用于自适应信号处理的FPGA实现。(The Verilog code about fir_pipline_lms and fir_rls. They commonly used in adaptive signal processing in FPGA platform.)
- 2021-05-06 20:58:37下载
- 积分：1
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Project_Gbit
pc与fpga之间通过千兆以太网交换机实现网络通信(Network communication between PC and FPGA via Gigabit Ethernet switch)
- 2020-06-17 20:40:04下载
- 积分：1
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AXI-HP-ZYNQ
用Vivado IPI搭建的Zynq-7000 PS到PL通信过程，使用了AXI-HP接口，利用AXI-DMA IP实现直接读写DDR的过程，软件可以配置传输尺寸。(The Zynq-7000 PS to PL communication process is built by Vivado IPI. AXI-HP interface is used, and AXI-DMA IP is used to read and write DDR directly. The software can configure the transmission size.)
- 2020-12-01 20:39:27下载
- 积分：1
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任意基数分频VERILOG代码，经过了编译，可以修改数字改变分频。...
任意基数分频VERILOG代码，经过了编译，可以修改数字改变分频。-Arbitrary base frequency Verilog code, after compilation, the figures can be amended to change the frequency.
- 2022-08-10 12:37:41下载
- 积分：1
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HB1
说明： 半带滤波器，用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)
- 2020-12-23 10:29:06下载
- 积分：1
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Farrow
说明： matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似。(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)
- 2021-03-28 22:29:11下载
- 积分：1
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欢迎大家使用该程序，是在FPGA下使用开发的。请大家使用。
欢迎大家使用该程序，是在FPGA下使用开发的。请大家使用。-Welcome to use the program is to use FPGA development. Please use the.
- 2022-06-19 03:41:34下载
- 积分：1
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VHDL_i2cs_rx_CPLD
CPLD imlementation of I2C BUS Controller.
The description has been made by VHDL
- 2012-08-20 14:30:18下载
- 积分：1
