登录
首页 » VHDL » 24秒倒计时系统(有跑马灯) 利用CPLD

24秒倒计时系统(有跑马灯) 利用CPLD

于 2022-03-26 发布 文件大小:284.75 kB
0 120
下载积分: 2 下载次数: 1

代码说明:

24秒倒计时系统(有跑马灯) 利用CPLD-24 seconds remaining systems (5,250) using CPLD

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • breath
    利用verilog写的PWM 程序,来实现产生呼吸灯的效果。(Using xerilog to generate breathing lamp)
    2020-06-17 04:40:01下载
    积分:1
  • PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛,本例用VHDL描述了一个锁相环作为参考,源码已经调试过...
    PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛,本例用VHDL描述了一个锁相环作为参考,源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上;顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
    2022-02-01 22:27:36下载
    积分:1
  • New FPGA
    基于FPGA的新型数据位同步时钟提取(CDR)实现方法-New FPGA-based data bit sync clock extraction (CDR) method
    2023-03-23 03:30:04下载
    积分:1
  • costas
    载波同步,costas环,基于Verilog的载波同步环(Carrier synchronization, costas ring, based on Verilog carrier synchronization ring )
    2021-03-05 13:09:31下载
    积分:1
  • line_four
    利用verilog HDL逐点比较法实现直线和圆弧插补(Use verilog HDL by-point comparison method to achieve linear and circular interpolation)
    2020-12-01 14:59:27下载
    积分:1
  • 8253
    8253可编程定时器/计数器芯片 VeriLog实现(8253 programmable timer/counter chip VeriLog achieve)
    2013-05-31 20:40:23下载
    积分:1
  • In this case is a convolutional code on a simple algorithm, using verilog HDL la...
    本例是关于卷积码的一个简单算法,用verilog HDL语言编写,整个文档包括了产生卷积的整个工程。-In this case is a convolutional code on a simple algorithm, using verilog HDL language, the entire document, including the method of deconvolution of the whole project.
    2022-02-05 20:03:55下载
    积分:1
  • fifo_rs232
    从FIFO到到RS232的实现,用于接收和缓存数据(TripAdvisor RS232 FIFO implementation for receiving data and cache)
    2016-08-26 13:57:23下载
    积分:1
  • VGA_Test
    说明:  基于FPGA的VGA驱动代码VHDL 在显示屏显示一个汉字(FPGA-based VHDL code of the VGA driver that a character in the display)
    2009-08-10 14:55:27下载
    积分:1
  • modelsim tutorial to learn only
    modelsim教程仅供学习-modelsim tutorial to learn only
    2022-12-19 07:25:03下载
    积分:1
  • 696518资源总数
  • 106174会员总数
  • 31今日下载