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用verilog HDL语言，通过一个4位移位寄存器实现一个信号转化为HDB3码并进行测试...
用verilog HDL语言，通过一个4位移位寄存器实现一个信号转化为HDB3码并进行测试
-Using verilog HDL language, through a 4-bit shift register realization of a signal into HDB3 code and test
- 2023-05-23 03:15:03下载
- 积分：1
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QAM
OFDM中的16QAM星座映射的实现实现详细代码(In OFDM 16QAM constellation mapping to achieve the realization detailed code)
- 2021-03-11 17:59:25下载
- 积分：1
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prepared using VHDL stepper motor control methods. For your reference.
用VHDL编写的步进电机控制方法.供大家参考用.-prepared using VHDL stepper motor control methods. For your reference.
- 2022-06-16 01:54:04下载
- 积分：1
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GPSDECODE
完成GPS的IRIG_B码解码，已经模块化，并且有详细的中文注释(Completed the GPS IRIG_B of decoding modular, and there are detailed notes in Chinese)
- 2021-04-07 16:09:01下载
- 积分：1
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FPGA
说明： 基于FPGA的数字式相位测量仪的设计与制作(FPGA-Based Digital Phase Meter Design and Production)
- 2010-04-16 19:40:41下载
- 积分：1
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这里面有许多vhdl的例子，相信对这语言的初学者受益匪浅
这里面有许多vhdl的例子，相信对这语言的初学者受益匪浅-There are many examples of vhdl, I believe that beginners benefit from this language
- 2023-06-28 10:40:04下载
- 积分：1
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median
说明： 用verilog编辑的中值滤波器！语言旁表有注释方便理解！(Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!)
- 2008-11-03 09:21:18下载
- 积分：1
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MB
说明： 基于VHDL语言数字秒表设计,在FPGA实验平台下开发(Digital stopwatch design based on VHDL, FPGA experimental platform under development)
- 2015-04-21 20:11:14下载
- 积分：1
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HART-HT2015
HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号，在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯，数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)
- 2013-07-16 17:23:16下载
- 积分：1
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DualPortRAM
此程序是Verilog HDL语言读写RAM的程序希望大家有用(This is Verilog HDL Promang)
- 2020-10-29 21:19:57下载
- 积分：1
