-
系统设计
基于PCF8591数模转换和DDS技术的信号发生器系统设计(Design of Signal Generator System Based on PCF8591 Digital-to-Analog Conversion and DDS Technology)
- 2020-06-21 02:20:01下载
- 积分：1
-
Xilinx-Timing
Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由(Xilinx FPGA timing constraint information, original, classic no reason)
- 2013-05-17 09:31:26下载
- 积分：1
-
vga编程。实现3种模式的vga控制，分别产生横彩条，竖彩条，棋格彩条的显示...
vga编程。实现3种模式的vga控制，分别产生横彩条，竖彩条，棋格彩条的显示-vga programming. Realization of the three-mode vga control, generate horizontal color of the color of the shaft, and the chess grid color of the show
- 2023-04-18 23:15:03下载
- 积分：1
-
二进制BCD码变换器采用VHDL
这是一个经过测试和使用的VHDL代码，用于将16位二进制输入数据转换为4位BCD。如果您直接驱动显示器而不经过处理器，并且希望显示在主程序中计算的参数，则该程序非常有用。有关转换的戏剧方面，请阅读随附的pdf。
- 2022-09-26 04:05:02下载
- 积分：1
-
Verilog-HDL-tutorial
verilog HDL经典的入门书籍，内容很详细，讲了许多实例，适合硬件描述语言初学者。(verilog HDL classic introductory book, the content is very detailed, spoke many instances, suitable hardware description language for beginners.)
- 2013-10-08 20:21:51下载
- 积分：1
-
ddr2_controller
A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.
- 2015-11-16 00:31:22下载
- 积分：1
-
navigation
Ship navigation project
- 2014-12-04 18:58:16下载
- 积分：1
-
本代码是实现了lwip协议栈,可以移植到其他类型的嵌如式操作系统上
本代码是实现了lwip协议栈,可以移植到其他类型的嵌如式操作系统上-This code is to achieve a lwIP protocol stack can be ported to other types of embedded operating systems such as the type
- 2022-03-18 10:40:22下载
- 积分：1
-
laplace
Laplace可以应用于图像的锐化，根据其原理，对于Laplace后的图像同样可以进行边缘检测。(Laplace can be applied to image sharpening. According to its principle, edge detection can also be performed for images after Laplace.)
- 2020-07-15 18:28:50下载
- 积分：1
-
8_1
一个具有置位、复位、左移和右移功能的八位移位寄存器/“01011010”序列检测器。移位寄存器电路端口为：异步清零输入端口rst，输入时钟clk，置数判断输入端口load，移位类型判断输入端口m，数据输入端口data[7:0]，输出端口q[7:0]。序列检测器电路端口为：异步清零输入端口rst，输入时钟clk，串行数据输入端口d，输出标志端口s。(A eight bit shift register / 01011010 sequence detector with set, reset, left shift, and right shift function. Shift register circuit port is: Asynchronous Clear input port rst, input clock CLK, set the number to determine the input port load, shift type to determine the input port m, data input port data[7:0], output port q[7:0]. The sequence detector circuit port is: Asynchronous Clear input port rst, input clock CLK, serial data input port D, output flag port s.)
- 2020-12-17 08:29:12下载
- 积分：1
