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豪华的CPU的VHDL代码的大学
DLX CPU VHDL CODE UNIVERSITY
- 2022-05-06 01:12:25下载
- 积分：1
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SVPWM_FPGA_ContainSourceCode
广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》，在详细分析经典SVPWM算法基础上，提出一种优化算法，并在FPGA上实现。论文附录包含VHDL源码。(Guangdong University Thesis " SVPWM algorithm to optimize its FPGA/CPLD realization" in the detailed analysis of the classical SVPWM algorithm is proposed based on an optimization algorithm, and implemented on FPGA. Paper appendix contains VHDL source code.)
- 2013-12-30 16:00:11下载
- 积分：1
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i2c
本文研究的IIC总线控制器具有如下特征
1.兼容飞利浦I2C标准，以主机模式与外围设备进行数据通信，对IIC从机模型进行读/读，读/写，写/写，写/读[18]。
2.多主操作
3.软件可编程时钟频率
4.时钟拉伸和等待状态生成
5.软件可编程确认位
6.时钟同步设计
7.仲裁中断丢失，自动转移取消
8.开始/停止/重复启动检测/确认生成
9.总线忙检测(The IIC bus controller studied in this paper has the following characteristics.
1. Compatible with Philips I2C standard, data communication between host mode and peripheral devices, read/read, read/write, write/write, write/read for IIC slave model [18].
2. Multiple Main Operations
3. Software programmable clock frequency
4. Clock stretching and waiting state generation
5. Software Programmable Confirmation Bit
6. Clock Synchronization Design
7. Loss of arbitration interruption and cancellation of automatic transfer
8. Start/Stop/Repeat Start Detection/Verification Generation
9. Bus busy detection)
- 2019-06-18 12:18:10下载
- 积分：1
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PWM
使用VerilogHDL语言加上IP核产生PWM调制波，占空比和频率可调。(The PWM modulation wave, duty cycle and frequency can be adjusted by using VerilogHDL language and IP kernel..)
- 2015-06-05 10:29:28下载
- 积分：1
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这是FPGA的Spartan 3E基础工程文件。该项目是基于VGA游戏…
this fpga spartan 3e based project file .the project is the game based on vga.
this file contains 2,20,25,400Hz clock generating file as per required for the project.-this is fpga spartan 3e based project file .the project is the game based on vga.
this file contains 2,20,25,400Hz clock generating file as per required for the project.
- 2023-02-25 10:20:03下载
- 积分：1
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这是本人写的可显示128*64LCD全屏汉字的程序,直接下到片子里即可出现象(需自己定制ROM).想显示第二屏的话只需加一个状态即可....
这是本人写的可显示128*64LCD全屏汉字的程序,直接下到片子里即可出现象(需自己定制ROM).想显示第二屏的话只需加一个状态即可.-I write this is the display of 128* Embedded full screen characters procedures, directly to the unit under the blankets will be out phenomenon (it-yourself customized ROM). to the second screen shows only the state can be a plus .
- 2022-04-07 10:48:15下载
- 积分：1
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一个简单的总线bus代码，初学者可以借鉴学习
一个简单的总线bus代码，初学者可以借鉴学习-A simple bus-bus code, beginners can learn to learn
- 2022-04-24 12:38:35下载
- 积分：1
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实验17 ADC实验
鉴于stm32在keil平台上的ADC采集转化，在LCD屏上显示程序(voltage acquisition adc)
- 2020-06-20 12:40:02下载
- 积分：1
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sigmoid_FPGA
sigmoid函数硬件实现，verilog代码及其测试用例(Sigmoid function hardware implementation, verilog code and test cases)
- 2017-05-08 20:36:04下载
- 积分：1
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c_xapp260
xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。(The use of Xilinx FPGA and Memory Interface Generator to simplify memory interface. This white paper discusses the various memory interface controller design challenges facing
Warfare and Xilinx solutions, but also explains how to use Xilinx
Software tools and hardware-proven reference designs to be for your own
With (from low-cost DDR SDRAM applications to such as 667 Mb/s
This higher performance DDR2 SDRAM interface) design a complete deposit
Storage device interface solution.)
- 2009-11-03 10:01:20下载
- 积分：1
