网站首页

这是FPGA的Spartan 3E基础工程文件。该项目是基于VGA游戏…

于 2023-02-25 发布文件大小:2.05 kB

 0  107

下载积分: 2 下载次数: 2

我要下载

代码说明：

this fpga spartan 3e based project file .the project is the game based on vga. this file contains 2,20,25,400Hz clock generating file as per required for the project.-this is fpga spartan 3e based project file .the project is the game based on vga. this file contains 2,20,25,400Hz clock generating file as per required for the project.

下载说明：请别用迅雷下载，失败请重下，重下不扣分！

发表评论

0 个回复

SYSTEMVIEWQPSK
使用 System view 编程 QPSK(use System Programming view QPSK)

2021-01-04 21:38:54下载

积分：1
TEXIO
TEXIO study testbench passed VHDL FPGA CPLD simulation Altera quartus

2015-03-21 23:19:21下载

积分：1
count23
一个简单的23计数器，用VHDL实现，可供初学者学习。(A simple 23 counters, with the VHDL implementation, available for beginners.)

2010-05-10 13:30:44下载

积分：1
9536
Xilinx user constraints file for the cpld xc9536 or xc9536xl or xc9572 or xc9572xl

2012-11-06 11:49:12下载

积分：1
my_SMG_Fengzhuang
FPGA 数码管接口例化编程，学习初级入门verilog编程技术(FPGA 数码管接口例化编程)

2015-01-05 20:43:50下载

积分：1
liftbd53
db53小波的verilog硬件实现源码(Wavelet db53 Verilog hardware source)

2008-06-26 10:42:23下载

积分：1
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0],...
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.

2022-06-13 02:00:08下载

积分：1
LCD_test
this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga

2013-07-25 14:43:43下载

积分：1
uart_slip
说明：实现串口通讯以及SLIP协议传输数据，增加了特殊字符的转义(Realization of Serial Communication and SLIP Protocol)

2021-01-19 18:58:41下载

积分：1
pn sequence generator
本设计是一个伪随机数发生器。此设计；

2023-02-23 15:45:04下载

积分：1

696518资源总数
105895会员总数
18今日下载

这是FPGA的Spartan 3E基础工程文件。该项目是基于VGA游戏…

0 个回复

热门标签

热门下载