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UART
本代码用verilog语言配合sopc和nios实现了串口调试的目的。软件编程用C语言描述，只是比较简单的例子，适合初学者做了解用，本人亲自在EP2C8Q上实践。(The code to use verilog language sopc and nios achieved with serial debugging purposes. Software programming using C language description, but relatively simple example for beginners to do with understanding, I personally EP2C8Q on practice.)
- 2013-09-11 10:48:17下载
- 积分：1
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CPU的VHDL设计代码
应用背景VHDL ；CPU设计...................................................................................................................................................................................................................................................................................................................................................................关键技术VHDL ；CPU设计...................................................................................................................................
- 2022-05-20 23:07:58下载
- 积分：1
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VHDL language used to write the VGA control procedures have been verified, the a...
用VHDL语言写的VGA 控制程序，已经验证过，绝对好用！-VHDL language used to write the VGA control procedures have been verified, the absolute ease of use!
- 2022-01-23 11:20:28下载
- 积分：1
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SPI_Code(Verilog)
SPI总线硬件描述语言Verilog下的实现，含主模式和从模式的实现，经过仿真验证，可作为一个单独的模块使用(SPI bus under the Verilog hardware description language to achieve with the main mode and slave mode realization, through simulation, can be used as a separate module uses)
- 2021-05-13 13:30:02下载
- 积分：1
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Image-Compress-FPGA_DSP
比较详细的阐述了图像压缩的原理,并基于DSP和VHDL实现该系统,最后在FPGA上通过.(More detailed exposition of the principles of image compress, and VHDL-based implementation of the system, and finally in the FPGA.)
- 2013-11-13 15:17:01下载
- 积分：1
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median
说明： 用verilog编辑的中值滤波器！语言旁表有注释方便理解！(Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!)
- 2008-11-03 09:21:18下载
- 积分：1
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AD9648_ver
FPGA通过SPI总线配置AD采集芯片AD9648的程序，Verilog实现 (FPGA configuration via SPI bus chip AD9648 AD acquisition procedures, Verilog realization)
- 2013-09-27 17:28:14下载
- 积分：1
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本源码为Nios II的开发示例,主要演示Nios II的I2C总线设计。开发环境QuartusII。
本示例十分经典，对基于SOPC开发的FPGA初学者有...
本源码为Nios II的开发示例,主要演示Nios II的I2C总线设计。开发环境QuartusII。
本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II I2C-bus design. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.
- 2022-05-20 17:06:23下载
- 积分：1
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pll
说明： fpga配置锁相环完整程序，使用quartus IP核，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)
- 2020-06-20 17:00:01下载
- 积分：1
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FIFO
Verilog HDL语言编写异步FIFO(Verilog HDL language, asynchronous FIFO)
- 2012-05-31 15:13:21下载
- 积分：1
