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RISC
说明: URISC的RTL级设计,Verilog代码(Design: URISC RTL Verilog)
- 2019-06-16 23:07:39下载
- 积分:1
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FPGA UART的发送等
FPGA UART transmit and so on
- 2022-01-24 13:54:39下载
- 积分:1
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本实验教程选用Xilinx公司的产品X9572,与之配套的开发软件为ISE4.1i,可进行原理图的输入和VHDL硬件描述语言的输入,并且可利用Modelsim进
本实验教程选用Xilinx公司的产品X9572,与之配套的开发软件为ISE4.1i,可进行原理图的输入和VHDL硬件描述语言的输入,并且可利用Modelsim进行功能仿真和时序仿真。-In this study, selected Xilinx tutorial products X9572, with supporting the development of software for ISE4.1i, schematic can be input and VHDL hardware description language input, and can use Modelsim functional simulation and timing simulation.
- 2022-03-21 02:07:25下载
- 积分:1
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VHDL描述的自定义交织器
交织器主要是对输入数据按照一定的规则打乱以便减少数据中过长的连0或者连1的出现。交织矩阵为行列矩阵,msgin为输入比特,msgout为交织输出比特,row和rol为交织器的行和列,可以通过改变col改变交织深度。先把输入的比特流数据改变为一个矩阵,再按照一定的方式输出为比特流数据
- 2022-03-15 22:36:53下载
- 积分:1
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a Verilog HDL language used in the preparation of multi
一个用VerilogHDL语言编写的多路解复用器-a Verilog HDL language used in the preparation of multi-channel demultiplexer
- 2022-02-06 11:12:06下载
- 积分:1
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索FPGA Verilog使用ROM和RAM实现高dcfifo
alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM
实现高速到低速时钟域的数据传输 ,值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
- 2023-05-06 14:25:03下载
- 积分:1
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基于CPLD的签到器的设计,用三维数组队人名进行储存
基于CPLD的签到器的设计,用三维数组队人名进行储存-Based on the attendance CPLD design, a few team names with three-dimensional storage
- 2023-01-07 09:45:04下载
- 积分:1
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I downloaded off the Internet and debug off, and the full realization of NIOS un...
本人上网下载下来并调试过的,完全实现NIOS 下对SD卡读写及包括FAT16文件系统的实现,使用的是QT8.1,FPGA里实现,里面有详细接线图,是完整的一个工程,在EP2C20Q240C8里调试成功-I downloaded off the Internet and debug off, and the full realization of NIOS under the SD card reader and includes FAT16 file system implementation, using QT8.1, FPGA years to achieve, which detailed wiring diagram, is a complete one project in EP2C20Q240C8 debug in the success of
- 2022-02-26 09:47:41下载
- 积分:1
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2通道ADC Ads527x的采集实现Vhdl
2通道模数转换器的采集实现。包含VIRTEX-II
和SPARTAN-III
两种类型的FPGA元件,模数转换器件为ADS527X系列,含仿真代码。采用VHDL语音实现,具有参考价值。
- 2022-01-20 23:16:05下载
- 积分:1
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altera_fft
verilog实际例子,非常适合初学者学习(verilog practical examples, very suitable for beginners to learn)
- 2020-12-06 16:49:22下载
- 积分:1